Constraint for a prime number

SystemVerilog
, ,
1

write a constraint to generate prime numbers between the range of 1 to 100?

2

Take a look at this previous question:

https://verificationacademy.com/forums/systemverilog/prime-numbers-constraint

This example also has a scecondary contraint that the number must contain a 7, which you would not need.

3 
class prime_numbers;
  rand int unsigned prime[];
  constraint const_prime {prime.size inside{100}; 

                          foreach(prime[i])
                            if (i>1 && (!((i%2==0 && i!=2) || (i%3==0 && i!=3)  ||  (i%5==0 && i!=5) ||  (i%7==0 && i!=7))))
                              prime[i]==i;
                          else
                            prime[i]==2;
                         }

  function void post_randomize;
    prime = prime.unique();
  endfunction

endclass

module tb();
  prime_numbers pm;

  initial
    begin
      pm=new();
      assert(pm.randomize());
      $display("the prime: %p",pm.prime);
    end
endmodule

Check this code.It may help you.

4

class cons;

rand int a;
int b;

// range constraint
constraint range { a inside {[1:100]}; }

// call function inside constraint
constraint prime_c { prime(a); }

// function to check prime
function bit prime(int x);

if(x <= 1)
  return 0;

for(int i=2; i<x; i++) begin
  if(x % i == 0)
    return 0;
end

return 1;

endfunction

function void post_randomize();

b = a;
$display("Prime number is %0d", b);

endfunction

endclass

module top;

cons c;

initial begin

c = new();

repeat(20) begin
  assert(c.randomize());
end

end

endmodule