Topics tagged casting

Topic	Replies	Views	Activity
Assignment rules for different width & sign SystemVerilog SystemVerilog , signed , casting , assignment	5	117	July 1, 2026
Can I static cast a "parameter int" to a "parameter string"? SystemVerilog SystemVerilog , parameter , casting	3	1112	March 15, 2023
Error on sequencer - send_request failed to cast sequence item UVM UVM , sequence , casting , uvm_fatal	9	2907	February 1, 2023
Question related to inheritance and classes SystemVerilog SystemVerilog , System-Verilog , OOPS , casting , Inheritance , cast	10	1891	October 15, 2022
Why void casting when randomizing class variables? SystemVerilog SystemVerilog , casting , radomize	2	661	April 29, 2022
Casting/copying uvm sequence item from parent class to derived class UVM UVM , casting , sequence-item	1	581	October 6, 2021
Casting in UVM UVM UVM , casting , cast	3	1613	April 6, 2021
How can I succesfully cast a string queue element to an enumerated data type? SystemVerilog SystemVerilog , casting , systemverilog-Arrays , beginner , casting-of-enum	1	1203	October 29, 2020
Casting int to string yields different results SystemVerilog SystemVerilog , casting	3	10698	June 14, 2020
[SV LRM-2017] Casting of structure to packed array example SystemVerilog SystemVerilog , casting	4	3060	May 28, 2020
Object handle casting versus assignment SystemVerilog SystemVerilog , casting	2	904	December 20, 2019
Implicit conversion of time to realtime? SystemVerilog SystemVerilog , casting , realtime , time	4	1962	August 19, 2019
Casting_static_casting_system_verilog SystemVerilog SystemVerilog , casting	3	1609	July 15, 2019
About casting ($cast) in system verilog SystemVerilog SystemVerilog , casting , cast	1	1345	February 7, 2018
Need Help in Casting in `uvm_info UVM UVM , uvm_info , casting	3	1963	February 9, 2017
Dynamic casting SystemVerilog SystemVerilog , casting	3	1903	July 12, 2016
System verilog Casting SystemVerilog SystemVerilog , casting	2	2035	February 26, 2016
Why results differs w/ and w/o declaring virtual methods in extended class SystemVerilog SystemVerilog , Polymorphism , casting , Virtual-methods , OOP	2	1710	December 18, 2015
Passing derived class transactions to a base class analysis port UVM UVM , casting , tlm_fifo , base-class , derived-class	2	2286	May 17, 2014