[SV LRM-2017] Casting of structure to packed array example

SystemVerilog
,
1

I used below code of LRM to understand casting but I am getting fatal error. something is wrong in code?

module abc;
  
  typedef struct {
    
    bit isfloat;
    union { int i; shortreal f; } n; // anonymous type
  } tagged_st; // named structure
  
  typedef bit [$bits(tagged_st) - 1 : 0] tagbits; // tagged_st defined above
  tagged_st a [7:0]; // unpacked array of structures
  
  initial begin
   static tagbits t = tagbits'(a[3]); // convert structure to array of bits
    $display("%p",t);
    a[4] = tagged_st'(t); // convert array of bits back to structure
    $display("%p",a[4]);
  end
endmodule

Error:-

** Fatal: Casting is only allowed on bit stream types.

Time: 0 ns Iteration: 0 Instance: /abc File: testbench.sv

Fatal error in file testbench.sv

2

In reply to juhi_p:

You cannot bit-stream cast a type containing a non-integral type (real), or a union; your example contains both. The rules are defined in section 6.24.3 Bit-stream casting in the IEEE 1800-2017 LRM.

3

In reply to dave_59:
But this one is example from SV LRM 2017, Page No. 134. Is it mean that this is gotcha?

4

In reply to juhi_p:

This example is a mistake in the LRM. It’s been reported in two places

https://accellera.mantishub.io/view.php?id=1445
https://accellera.mantishub.io/view.php?id=2312

5

In reply to dave_59:
Got it,thanks.