Topics tagged systemverilog-Arrays

Topic	Replies	Views	Activity
Pattern Detector 10110 in SV (no FSM) SystemVerilog SystemVerilog , testbench , System-Verilog , SV , queue , systemverilog-Arrays , queues-systemverilog	1	458	February 19, 2025
Using sum() to Calculate the Sum of a 2D Array SystemVerilog SystemVerilog , systemverilog-Arrays	11	2410	May 28, 2025
Initializing a multi-dimentional array to all zeros SystemVerilog SystemVerilog , Multi-dimensional-arrays , systemverilog-Arrays	3	8705	May 15, 2025
Need help with understanding which data structure is good to implement this case SystemVerilog Dynamic-Array , Parameters , systemverilog-Arrays , array-of-structures	4	377	January 29, 2024
Randomize a 2-dimensional array to generate below pattern: SystemVerilog SystemVerilog , contraint , systemverilog-Arrays , systemverilogmultidimentional-arraya-memory , Randmization-with-array-reduction	4	1372	January 16, 2024
Sum of array (array constraints) SystemVerilog SystemVerilog , systemverilog-Arrays	2	766	January 11, 2024
Count unique values in an array or a queue SystemVerilog SystemVerilog , unique , systemverilog-Arrays , systemverilog-constraint , queues-systemverilog	4	1045	November 3, 2023
How to set a register to a value thru a hierarchy receiving as string? UVM UVM , RAL , accessing-the-associative-array-elements , systemverilog-Arrays	3	715	October 4, 2023
Passing array size as argument for another array inside the task/function SystemVerilog SystemVerilog , parameter , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	3	965	June 20, 2023
What causes the failure of the randomization process? SystemVerilog SystemVerilog , randomization , systemverilog-Arrays	3	719	June 19, 2023
Comparing Variable slices of Fixed Arrays SystemVerilog SystemVerilog , systemverilog-Arrays , compare	9	5972	May 22, 2023
Constraint for two dimensional array SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays , lowertrianglematrix-systemverilog-constraint	16	3154	May 7, 2023
Randc in an variable within an array of objects UVM UVM , randc , systemverilog-Arrays	11	2993	May 2, 2023
Generate NXN Matrix with following rules SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes , square-matrix , constraint-dynamic	2	678	April 26, 2023
How to create random dynamic 2D arrays in SystemVerilog? SystemVerilog SystemVerilog , systemverilog-Arrays	12	1798	December 5, 2022
How do I define an associative array of queues? SystemVerilog SystemVerilog , associative-array , Queues-in-system-verilog , systemverilog-Arrays	15	16568	August 19, 2022
Arranging zeroes in an array at odd indices SystemVerilog SystemVerilog , logic , systemverilog-Arrays , uvm-packed-unpacked-array-SV	3	953	May 2, 2022
Printing non-unique elements in an array SystemVerilog SystemVerilog , logic , systemverilog-Arrays	1	707	April 16, 2022
Question on Array.Sum() Method , generate a n*n matrix such that there is only one 1's in a coloumn SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays	8	1573	March 14, 2022
How to use variable for forcing the path SystemVerilog SystemVerilog , systemverilog-Arrays	4	1348	March 11, 2022
Array constraint. Each row total should be 100, with each element less than 80. I want to understand how to do this using only sum method of array SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	9	1879	February 25, 2022
Passing Unpacked Array of Packed Array as task arguments SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	1	1357	February 23, 2022
What {(a+1)}[7:0] implies inside conditional statement? SystemVerilog SystemVerilog , systemverilog-Arrays , conditional-statement , bit-array , ternary , bit-slicing	1	772	February 2, 2022
Constraint for repeating numbers in an array in a unique pattern SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays	6	2230	January 28, 2022
Foreach usage in randomization constraints SystemVerilog SystemVerilog , constraint-randomization , constraint-foreach-loop , constrained-random-generation , systemverilog-Arrays , constraint-dist	12	8554	November 7, 2021
Reverse an array without using the reverse() function SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-Arrays-logics	2	3396	October 28, 2021
Associative array duplicate items SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	1	1593	October 27, 2021
Constraint randomization for two address regions SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays , systemverilog-arrays-struct-constraint-randomization-indexes	3	1551	August 5, 2021
Finding repeated items in a array using array manipulation methods SystemVerilog SystemVerilog , systemverilog-Arrays , array-manipulation-methods , array-system-verilog-uvm , array-manipulation-method	5	2143	August 4, 2021
Regarding class array inside another class SystemVerilog SystemVerilog , systemverilog-Arrays	6	1255	August 3, 2021