Implicit conversion of time to realtime?

SystemVerilog
, , ,
1

Are there any implicit casting rules for converting time to realtime?

2

In reply to prang:

These are built-in types and follow all the same conversion rules.

typedef logic [63:0] time;
typedef real realtime;
3

In reply to dave_59:

As per the LRM section 6.12.2
Implicit conversion shall also take place when an expression is assigned to a real. Individual bits that are x or z in the net or the variable shall be treated as zero upon conversion.

Should I take this to mean, yes I can directly assign time to realtime, without the need for an explicit cast?

4

In reply to prang:

Yes, you can go between integral and real without a cast, but using an explicit cast shows your intent better.

5

In reply to dave_59:

Thanks!