Object handle casting versus assignment

SystemVerilog
,
1

Hi,

How is casting an object handle different from assigning the handle ? As I understand, casting is an assignment with an additional compatibility check. Is that correct ?

Example:-
line1: parent_handle = child_handle;
line2: if (!($cast(child_handle,parent_handle))) $error(“cast error”);
line3: child_handle = parent_handle;

In the above example, either having just line 2 or line 3 alone should result in the same behavior. Is that correct ?

Regards
Amith

2

In reply to amithjohnthomas:

https://verificationacademy.com/forums/systemverilog/confusion-over-casting-classes#reply-38010

3 

//this is legal, type compatibility will be checked during run time 
line2: if (!($cast(child_handle,parent_handle))) $error("cast error");

//this isn't legal, compile error.
line3: child_handle = parent_handle;