Casting_static_casting_system_verilog

SystemVerilog
,
1

Hi All,

Please advice for SV casting;

  1. static_type_conversion;
int a;
real b;

initial begin
  //real to int
  a = int ' (3.14);     //line1
  $display("1 INT = %0d", a);

  a = 3.14;     //line2
  $display("2 INT = %0d", a);
end

////////output
1 INT = 3
2 INT = 3

with casting, we will get output 3. But we are getting same result also with line2, that is without casting, due to implicit conversion. Then for what purpose are we using type (one type to another data type) conversion ?

  1. static_size_conversion;
int unsigned num;
logic  [7:0] a;

initial begin
a = 8'(num); // Reduce integer (32bit) to 8bit

num = 16'd300;
  $display("3 INT = %0d", num);
end

////output
3 INT = 300

Here, I converted num from 16bit to 8 bit, 2^8=256, it means it should have only maximum of 255. But how come, num is taking more than 8bit value, size conversion is unsuccessful … ?

Could anyone suggest casting for size and type conversion with example usage ?

Thank You,
Mahesh

2

In reply to Mahesh K:

Static casting is usually used when you want some other cast different from the implicit casting rules. But you can use an explicit cast to show your intent even the cast is the same as what would happen implicitly. This might eliminate error from linting tools.

In your second example, your explicit cast to 8 bits is what would implicitly happen without the cast. But you made the assignment to num after the cast.

3

In reply to dave_59:

Hi Dave,

  1. static_size_conversion;
    My intention is to convert num of 32 bit into 8 bit. After casting, num should accept only up to 255 as a maximum value for 8 bit number, but if I randomize also, its taking as 32 bit number, then looks like conversion is unsuccessful. Any reason/example to share ?

Thank You,

4

In reply to Mahesh K:

Hi Mahesh,
The type of variable num is NOT getting converted to an int of size 8 bit. The casting applies only while assigning num to a.

Dave, Please correct me if I am wrong.

Regards