Assertion inside clocking block in SystemVerilog

[laureen.giac]

Hi

Can anyone tell me please if the following is legal?

clocking cb1 @(posedge clk);
property p1;
(counter != 0);
endproperty

assert property(p1)
else begin
repeat(5)@(posedge clk)
$error(“testing mce_wait feature…”);
end

endclocking // cb1

Can I have an assert statement inside a clocking block?

[rshrig]

Not sure, if its legal.

Nevertheless, I am curious as to why you want have assertions within a clocking block…

In “my opinion” clocking block helps in :

1. Avoiding race condition b/w RTL & Testbench codes.
2. Introducing skew which helps in convenient waveform inspection + point #1 benefit.

In reply to laureen.giac:

[ben2]

In reply to rshrig:
The syntax found in 1800 defines what is legal. Specificaly,

clocking_item ::=
default default_skew ;
  | clocking_direction list_of_clocking_decl_assign ;
  | { attribute_instance } assertion_item_declaration

assertion_item_declaration ::=
  property_declaration
  | sequence_declaration
  | let_declaration

// Note that declarations are NOT assertion statements that include: 
concurrent_assertion_statement ::=
  assert_property_statement
  | assume_property_statement
  | cover_property_statement
  | cover_sequence_statement
  | restrict_property_statement

 

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