Assertion inside clocking block in SystemVerilog

Not sure, if its legal.

Nevertheless, I am curious as to why you want have assertions within a clocking block…

In “my opinion” clocking block helps in :

  1. Avoiding race condition b/w RTL & Testbench codes.
  2. Introducing skew which helps in convenient waveform inspection + point #1 benefit.

In reply to laureen.giac: