Why are clocking blocks preferred when when we want to drive and sample stimulus in a SystemVerilog testbench?

SystemVerilog
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1

I have seen multiple testbench codes where the driving of stimulus and the sampling are done using clocking blocks. Why is this so? Are there some pitfalls in using the interface directly to drive and sample stimulus?

2

In reply to vk7715:

https://verificationacademy.com/forums/systemverilog/assigning-interface-net-type-signals-class

3

In addition to Ben’s answer , here are links for SNUG Paper on Clocking Blocks :
SNUG_Austin_2012_paper51_presentation
paper51_taming_tb_timing_FINAL_fixes