Topics tagged systemverilog-interface

Topic	Replies	Views	Activity
Why does using a generic interface port (without modports) allow both dut0 and dut1 to drive data and enable without error, while using modports enforces directionality and prevents such assignments? SystemVerilog systemverilog-interface	0	59	March 21, 2025
Placing Assertions in Interfaces SystemVerilog SystemVerilog , SVA-Assertion , systemverilog-interface	0	319	June 4, 2024
False posedge event indication on a signal SystemVerilog Clocking-Block , systemverilog-interface	1	174	February 16, 2024
How to use config_db get() and set method to send array of interfaces? SystemVerilog SystemVerilog , systemverilog-interface , uvm-config_db	5	1650	July 25, 2022
Assign to interface input inside Class SystemVerilog SystemVerilog , class , interface , systemverilog-interface , assignment	3	623	June 14, 2022
How to connect multiple interface within dut in UVM? UVM UVM , systemverilog-interface	10	3242	February 19, 2022
Hypothetical question : what if there are major updates in my interface, creating new interface with different name but don't want to touch Driver & Monitor code UVM SystemVerilog , UVM , systemverilog-interface	2	812	January 22, 2022
Monitor the toggling of interface siganls SystemVerilog SystemVerilog , systemverilog-interface	1	549	July 13, 2021
Parameterizing the Bit Widths of fields in a packed struct so that modules can infer bit width if used in port map - virtual interface - interface - compile time configured struct bit width SystemVerilog SystemVerilog , systemverilog-interface	4	2341	January 7, 2021
Binding modules with systemverilog interface SystemVerilog SystemVerilog , bind , Bind-Interface-failed , systemverilog-interface	4	18771	September 4, 2020
How do I use buf or nmos build in modules inside interface SystemVerilog SystemVerilog , I2C-protocol , systemverilog-interface , Build-in-module	1	891	July 6, 2020
How to connect interface ports to VHDL module ports SystemVerilog SystemVerilog , systemverilog-interface , VHDL-SystemVerilog	3	1440	April 13, 2020
Interface based Query SystemVerilog SystemVerilog , interface , systemverilog-interface , actual-interface	1	787	February 4, 2020
UVM clock Agent UVM UVM , uvm_sequence , uvm-interface , uvm_agent , systemverilog-interface	7	4352	December 5, 2019
Systemverilog interface connect Error-[SV-UIP] SystemVerilog SystemVerilog , systemverilog-interface	2	6802	April 17, 2019
Virtual interface usage in package SystemVerilog SystemVerilog , systemverilog-interface	1	1857	February 14, 2017