Systemverilog interface connect Error-[SV-UIP]

SystemVerilog
,
1

Hi there,
I’m a newer with the usage of system verilog “interface”.
Followings is my explanations and codes.

step 1. Define a interface as “IN_DATA_IF”.
step 2. Build a module “DATA_MODULE” that have a “IN_DATA_IF” listed in its i/o port
step 3. At top bench, I forget to instantiation “DATA_MODULE”.

And vcs shows [Error-[SV-UIP] Unconnected interface port, the port “data_if” of top-level module “DATA_MODULE” whose
type is interface IN_DATA_IF is left unconnected. It is illegal to leave the interface ports unconnected.
Please make sure that all interface ports are connected.]

step 4. instantiation “DATA_MODULE”. the error is pass.

/* ====================================== */
interface IN_DATA_IF
  logic             i_valid;
  logic     [11:0]  i_data ;
endinterface: IN_DATA_IF
/* ====================================== */

/* ====================================== */
module DATA_MODULE (
    input           clk,
    IN_DATA_IF      data_if
    );
    .....
endmodule //DATA_MODULE
/* ====================================== */

module top_bench;
  logic   clk, rst;
  IN_DATA_IF  top_data_if;

  //DATA_MODULE(.clk(clk)
  //            .data_if(top_data_if()
  //           );
endmodule //top_bench
2

In reply to vatics_r89162:
The error is because some tools automatically instantiate any module you compile as a top-level module if not instantiated anywhere else. So when you forget it adds it back.

You should always check to make sure your simulation has only the top-level modules you think it should have.

3

In reply to dave_59:

Dear Dave_59,
Sorry, I did’t leave the code well before. Actually, I have a define DATA_MODULE_ENABLE to instantiation DATA_MODULE or not.

/* ====================================== /
module DATA_MODULE (
input clk,
IN_DATA_IF data_if
);
…
endmodule //DATA_MODULE
/ ====================================== */

module top_bench;
logic clk, rst;
IN_DATA_IF top_data_if;

ifdef **DATA_MODULE_ENABLE** DATA_MODULE(.clk(clk) .data_if(top_data_if() ); endif //DATA_MODULE_ENABLE
endmodule //top_bench

According your suggestion, maybe I have some solutions

  1. use `ifdef DATA_MODULE_ENABLE to enclosed the DATA_MODULE
  2. assign specific top module in vcs
  3. find a vcs parameter to ignore this error ( I found “allow_unconn_interface_port” in doc. but I did’t try it yet.