Binding modules with systemverilog interface

SystemVerilog
, , ,
1

Hi,
I have doubt regarding binding interface with module in system verilog.

I have one input port and one output port in my dut module

module dut(input clk, output req);
endmodule

Interface I have written like this:

interface trace_interface (
    input fsm_main_clk,
    input type_MainConfInterface fsm_main_mainconf

);

I have one more module trace_file where I need to get the value from interface which is taken from DUT.

module trace_file(input mainconf, input type_MainConfInterface mainconf);
endmodule

In my top file I used binding as like this :

bind dut trace_interface trace_if(.fsm_main_mainconf(req), .fsm_main_clk(clk));
bind trace_file trace_interface trace_if(.fsm_main_mainconf(mainconf), .fsm_main_clk(clk));

How can I connect these two modules through interface and binding? Since clk is input to two modules how can I connect both of those?

2

Please use code tags making your code easier to read. I have added them for you.

You cannot bind a module inside in interphase, so you need to make them both modules or both interfaces.

The port definitions of trace_file do not match the bind instantiation. Does trace_file really need to be underneath trace_interface, or can they both be bound into the dut?

3

In reply to dave_59:

Hi,
Thank you very much Dave for the help.

The port definitions of trace_file do not match the bind instantiation. >> SOrry it was a mistake form my side.

module dut(input clk, output type_MainConfInterface req);
endmodule

module trace_file(input clk, input type_MainConfInterface mainconf);
endmodule

I will explain my requirement. I want to get the two signals in DUT to my trace_file module through an interface. SO what I was thinking is that first I will bind the DUT with my interface and then the bind the same interface with trace_file module. Is this possible?

Also I referred one earlier post in verification academy and I tried to create like this and its not working in my case.

Bind interface to the instance of RTL top - SystemVerilog - Verification Academy

4

In reply to rr2007:

As I said before, you cannot put an instance of a module inside the instance of an interface. It doesn’t matter if you directly instantiate it or use bind to instantiate. From what little code you have shown, I don’t see why you don’t just find your module and interface directly into the dut. It would help if you could explain what “not working” means. Are you getting a compiler error, or getting results different from what you were expected?

5

In reply to dave_59:

Not working means I am not getting the signal values in DUT to my interface signals.
Actually this DUT is an instance which is inside mydesign like eg, instance1.fsm.DUT
from this hierarchy I need to get some port signal values to my interface . That is my aim.Then use it inside trace_file module.
I can directly probe like instance1.fsm.DUT.clk, but I think its not a good way of accessing signals which lies inside another module

As I said before, you cannot put an instance of a module inside the instance of an interface. It doesn’t matter if you directly instantiate it or use bind to instantiate >> But in LRM page 741 I am seeing binding interface in module as like below

Binding of a module instance or an interface instance works the same way as described for the previous

programs.

interface range (input clk, enable, input var int minval, expr);
property crange_en;
@(posedge clk) enable |-> (minval <= expr);
endproperty
range_chk: assert property (crange_en);
endinterface
bind cr_unit range r1(c_clk,c_en,v_low,(in1&&in2));

In this example, interface range is instantiated in the module cr_unit. Effectively, every instance of
module cr_unit shall contain the interface instance r1.