In reply to dave_59:
Hi,
Thank you very much Dave for the help.
The port definitions of trace_file do not match the bind instantiation. >> SOrry it was a mistake form my side.
module dut(input clk, output type_MainConfInterface req);
endmodule
module trace_file(input clk, input type_MainConfInterface mainconf);
endmodule
I will explain my requirement. I want to get the two signals in DUT to my trace_file module through an interface. SO what I was thinking is that first I will bind the DUT with my interface and then the bind the same interface with trace_file module. Is this possible?
Also I referred one earlier post in verification academy and I tried to create like this and its not working in my case.
Bind interface to the instance of RTL top - SystemVerilog - Verification Academy