Binding modules with systemverilog interface

In reply to rr2007:

As I said before, you cannot put an instance of a module inside the instance of an interface. It doesn’t matter if you directly instantiate it or use bind to instantiate. From what little code you have shown, I don’t see why you don’t just find your module and interface directly into the dut. It would help if you could explain what “not working” means. Are you getting a compiler error, or getting results different from what you were expected?