Topics tagged uvm

Topic	Replies	Views	Activity
Common uvm_sequence for multiple sequence_items UVM uvm_sequence_item , uvm_sequence	3	160	May 19, 2025
Non-compute-intensive way to add an asynchronous delay to a transaction UVM SystemVerilog , UVM , System-Verilog , driver , uvm_sequence	1	86	April 25, 2025
Sequence not started got casting error for p_sequencer and m_sequencer UVM SystemVerilog , UVM , sequencer , uvm_sequence	5	324	March 6, 2025
Dynamic sequence from command line UVM SystemVerilog , UVM , uvm_sequence , dynamic-seq	5	213	March 1, 2025
How to grab the sequence in middle to stop any transactions further until ungrab() UVM UVM , sequence-control , uvm_sequence , grab-ungrab-stop_sequences	6	242	February 19, 2025
Uvm_do_on running sequence on multiple sequencers directly UVM sequence , uvm_sequence , InterviewQuestions	3	218	February 13, 2025
How to end background reg access sequences gracefully UVM SystemVerilog , testbench , uvm_sequence	1	177	September 11, 2024
Do we need get_full_name() in sequence item creation? If so, why? UVM UVM , uvm_sequence , UVM_CREATE-UVM_SEQUENCE , get_full_name , uvm_sequence-body	3	1440	August 8, 2024
Is it valid to pass uvm_component parameter while creating instance of a sequence? UVM uvm_sequence , seq	6	364	March 30, 2024
Uvm_sequence randomization UVM UVM , uvm_sequence , randomization	4	2474	April 24, 2023
Uvm_sequence without #(seq item) UVM UVM , uvm_sequence	2	776	March 4, 2023
Neither the item's sequencer nor dedicated sequencer has been supplied to start item in m_bseq UVM UVM , uvm_sequence , UVM-sequencer-p_sequencer , start_item-in-the-extended-class	4	3391	February 19, 2023
Fork join threads in a sequence body UVM UVM , uvm_sequence , fork_join , thread-fork	4	1236	February 17, 2023
Adding additional ports to driver/sequencer pair UVM UVM , uvm_sequence , uvm_sequencer , uvm-uvm_driver- , UVM-DRIVER-INTERFACE	1	678	November 10, 2022
Uvm sequence stop isn't working UVM UVM , uvm_sequence	3	800	May 3, 2022
Concurrent calls to get_next_item() not supported. Consider using a semaphore to ensure that concurrent processes take turns in the driver UVM UVM , sequencer , uvm_sequence , fork-join	1	1795	December 21, 2020
Two different logic in single driver UVM UVM , uvm_sequence , uvm-uvm_driver	8	1381	November 16, 2020
Sending Value from Driver to Sequence UVM UVM , uvm_sequence , uvm-uvm_driver-	1	796	October 10, 2020
Incompatible class assignment error UVM UVM , uvm_sequence , ParameterizedClass	3	1524	September 25, 2020
UVM clock Agent UVM UVM , uvm_sequence , uvm-interface , uvm_agent , systemverilog-interface	7	4438	December 5, 2019
How to access a variable which is in driver or scoreboard (or any classes derived from uvm_components) from sequence class? UVM UVM , uvm_sequence	1	1399	July 14, 2019
How to use wait fork statement in nested fork join_none block SystemVerilog SystemVerilog , uvm_sequence , fork-join_none-multiple-threads , fork-join	2	3577	May 31, 2019
The best way to start/select sequence(s) in a test class UVM UVM , sequences , virtual-sequencers , uvm_sequence , virtual-sequences , sequence-api	4	3899	July 9, 2018
Preventing a particular sequence to execute of the parent class from the Child class UVM UVM , Method-Overriding , uvm_sequence	1	1219	June 21, 2018
$time in sequence UVM UVM , uvm_sequence , time	2	1830	June 21, 2018
Hidden arguments when calling sub-sequence's task UVM UVM , uvm_sequence , Calling-Sequence-inside-a-sequence , hierarchical-task-call	7	2426	March 14, 2018
Question related to uvm_sequence input UVM UVM , uvm_sequence_item , uvm_sequence	1	1334	March 12, 2018
Can I pass variable from uvm_sequence to test class? UVM UVM , config_db , uvm_sequence , UVM-uvm_test	2	1525	February 22, 2018
How to randomly pick a valid sequence_item and form a sequence UVM UVM , uvm_transaction , uvm_sequence	5	1938	July 21, 2017
Access testbench top signal in test or sequence UVM UVM , uvm_sequence , UVM-uvm_test , root	1	3518	July 6, 2017