Access testbench top signal in test or sequence

UVM
, , ,
1

Hi,

I want to access the reset signal from testbench top level in test or sequence. In testbench I have the reset signal declared as

module top;
reg rst;
...
initial begin
   rst = 1'b0;
   #10;
   rst = 1'b1;
end 

v_intf intf(clk,rst); // interface instance

initial begin 
    uvm_config_db#(virtual v_intf)::set(null,"*","intf",intf);
    run_test();
end
endmodule

I want to access this “rst” signal in my test/sequence (any solution is fine). How can I access “rst” so that I can set value after my sequence completes.
So in my test after seq.start(env.agent.sqr) completes then I want to access this “rst” signal to set value. I tried

class base_test extends uvm_test;
...
virtual v_intf intf;
...
virtual function void build_phase();
     super.build_phase(phase);
    if(!uvm_config_db#(virtual v_intf)::get(this,"","intf", intf))
        `uvm_error(get_type_name,"not got interface handle")
endfunction

virtual task run_phase(uvm_phase phase);
  phase.raise_objection(this);
  fork
  seq.start(env.agent.sqr);
  ...
  join 
  $root.intf.rst = 1'b0  //error here, i want help with this line 
   phase.drop_objection(this);
endtask

endclass

but didn’t work for me. I got error saying,

*E,ILLHIN illegal location for a hierarchical name (in a package)

Thank you.

2

In reply to rakesh2learn:

To access signals, you should create an interface and connect the interface to the required signals. Read/Drive the signals using a sequence/driver combination. This is normally accomplished by creating an agent.