Common uvm_sequence for multiple sequence_items

UVM
,
1 

HI All, 

one uvm_sequence parameterized with multiple sequence items. 
For example, 

class my_sequence1 extends uvm_sequence #(usb_seq_item);
class my_sequence1 extends uvm_sequence #(pcie_seq_item);

Is this allowed? If yes, could you please tell me the use case. 
I tried to find example for this, but couldn't. 

Thank you,
2

SystemVerilog does now allow two identifiers declared with the same name in the same scope. Doesn’t matter if the identifier is a class type or variable.

3 
 class base_seq_item extends uvm_sequence_item;
   `uvm_object_utils(base_seq_item)
   function new(string name = "base_seq_item");
     super.new(name);
   endfunction
 endclass
 
 class usb_seq_item extends base_seq_item;
   rand bit[7:0] data;
   `uvm_object_utils(usb_seq_item)
   function new(string name = "usb_seq_item");
     super.new(name);
   endfunction
 endclass
 
 class pcie_seq_item extends base_seq_item;
   rand bit[15:0] addr;
   `uvm_object_utils(pcie_seq_item)
   function new(string name = "pcie_seq_item");
     super.new(name);
   endfunction
 endclass
 
 class my_sequence1 extends uvm_sequence #(base_seq_item);
   `uvm_object_utils(my_sequence1)
   function new(string name = "my_sequence1");
     super.new(name);
   endfunction
   task body();
     base_seq_item item;
     repeat(5) begin
       if ($urandom % 2 == 0) begin
         item = usb_seq_item::type_id::create("usb_item");
       end else begin
         item = pcie_seq_item::type_id::create("pcie_item");
       end
       start_item(item);
       assert(item.randomize());
       finish_item(item);
     end
   endtask
 endclass

A uvm_sequence cannot be parameterized with multiple sequence item types directly, as it accepts only one type. To handle multiple types like usb_seq_item and pcie_seq_item, use a common base class (base_seq_item) for the sequence items. The sequence can then dynamically create and send either type of item based on runtime conditions.

4

Yes, Thank you for the example.