Topics tagged driver

Topic	Replies	Views	Activity
Driver with DUT's output UVM driver	2	167	August 20, 2025
Non-compute-intensive way to add an asynchronous delay to a transaction UVM SystemVerilog , UVM , System-Verilog , driver , uvm_sequence	1	77	April 25, 2025
Driver Response to Sequence UVM UVM , sequencer , driver	7	1189	March 7, 2024
Need to drive a condition after item_done() UVM UVM , driver , uvm-uvm_driver	1	361	October 18, 2023
Verification of components containing PHY IP UVM UVM , driver , phy	2	713	September 14, 2023
Get_next_item is blocking. how do get a clock sampled data from driver? UVM UVM , driver , get_next_item	3	699	January 29, 2023
Get_response function in sequence does not get unblocked after put_response UVM UVM , sequence , get_response , driver , systemverilog-uvm	2	1310	February 3, 2022
How to track a changes in a sequence in a UVM testbench? UVM UVM , driver , uvm-sequence-item , UVM-Sequence-Tracking	1	1024	January 28, 2022
Passing queue through sequence_item UVM UVM , sequencer , sequence , driver , Queues , sequence-item	2	1421	January 22, 2022
Can the monitor communicate with the sequence directly? UVM UVM , driver , TLM-ports , Generating-sequences	17	11900	December 7, 2021
Response driver UVM UVM , driver	2	894	October 13, 2021
Problem running a reactive sequence in a forever loop UVM UVM , driver , reactive-sequence , fork-join , forever-block	5	2021	April 27, 2021
Forked process being killed in a SV TB SystemVerilog SystemVerilog , driver , clocking-block-assignment	1	699	April 20, 2021
Driver , Sequencer N Sequence Parameterization UVM UVM , driver , Sequencer-N-Sequence-Parameterization	5	1622	February 4, 2021
Driving DUT internal signals with bind module UVM UVM , bind , DUT , driver , internal-signal-in-DUT , internal-signal	2	2098	October 24, 2020
Support back to back transactions in UVM driver UVM UVM , driver , back-to-back , b2b	12	4879	October 23, 2020
How to drive a reg/integer in a dut so as to avoid the error of Illegal combination of structural and procedural drivers UVM SystemVerilog , UVM , bind , interface , driver	1	4656	June 8, 2020
Advance time in uvm_driver UVM UVM , driver , clock , data-flow-synchronization	5	1376	May 21, 2020
Synchronization problems in uvm_driver SystemVerilog SystemVerilog , UVM , driver , clockingblock	4	1397	April 27, 2020
How to introduce a fixed time delay between driver and checker? SystemVerilog SystemVerilog , checker , driver , clocking-block-testbench	1	879	April 10, 2020
Implement transaction logic in driver or sequence class UVM UVM , sequence , driver	12	2194	April 1, 2020
Debugging sequence/driver communication UVM UVM , driver	10	3608	January 17, 2020
Multiple sequencers to a single driver UVM UVM , virtual-sequencer , driver , sequencers	12	5931	August 20, 2019
How to drive data that might contain part of two packets? UVM UVM , driver	7	1544	July 25, 2019
What are the key points when implementing Driver? UVM UVM , driver	17	2030	July 21, 2019
Dont drive a value to virtual interface in uvm driver UVM UVM , error , sequence , driver , virtual	5	2008	June 25, 2019
Driver handshaking UVM UVM , driver	1	1300	August 10, 2018
Get the status of a sequence UVM UVM , sequencer , sequence , driver	6	3997	July 30, 2018
Driver with two sequencer UVM UVM , sequencer , driver , item , ports	2	3569	March 25, 2016
What is the difference between driver and BFM? UVM UVM , driver , BFM	2	12233	March 21, 2016