Verification of components containing PHY IP

UVM
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I apologize in advance for a slightly abstract question.
I am developing network components, which, as a rule, contain third-party IP cores for the configuration of transceivers (Ethernet PHY, PCIe PHY). Recently I started using UVM for project verification (top-level system tests), but there is no complete understanding of how to properly verify projects that contain third-party IP.
On the one hand, the DUT contains serial ports from PHY and it would be appropriate to write a UVM driver for them. But on the other hand, it is quite time-consuming to implement the physical layer in the driver and actually does not make sense, since the cores have already been verified.
That leaves me with two options:

  1. Bypass the physical layer in the DUT, that is, modify its top layer of the component specifically for verification and create auxiliary ports to which the driver implementing the channel layer will connect. Which in my opinion is not very correct, because I want to indirectly test the interaction of logic with the PHY IP.
  2. Somehow integrate the PHY IP itself into the test environment.

Which approach is more appropriate? Perhaps there are some articles discussing this point in UVM context?

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In reply to DefaultName:

Just because you think your third-party IP’s have been verified doesn’t absolve you from verifying that you are using it correctly.

If you have performance concerns, you might want to replace the PHY on most of your tests with a higher level models that just has the functionality to interact with your DUT.

Probably not the answer you were looking for, but I hope this helps.

3

In reply to dave_59:

Thank you for the answer.
I came across an article that, it seems to me, analyzes this problem and suggests a way: Integration of HDL Logic inside SystemVerilog UVM based Verification IP.