How to introduce a fixed time delay between driver and checker?

SystemVerilog
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1

I have a situation: where I assert a val signal when a transaction is driven. It goes through a fixed pipelined design and then I want to trigger a checker module at the output. Initially had input_val and out_val signals, where out_val sig is assigned in the design:

always_ff @(posedge clk) begin
    if ( reset ) begin
        foreach(valid_pipe[i]) valid_pipe[i] <= '0;
    end else begin
        valid_pipe[0] <= i_val;
        for ( int i = 1; i < PIPE_DELAY; i++ ) begin
            valid_pipe[i] <= valid_pipe[i - 1];
        end
    end
end
assign  o_val                      = valid_pipe[PIPE_DELAY - 1];

But my intention is to not involve the design to calculate the o_val, instead want the testbench to take care of it. Can someone please guide me ?

PS: The testbench is a simple driver/checker/generator model linked with the design using interfaces. No UVM involved

2

In reply to kb646bits:

We don’t now anything about your design or how the interfaces work to the DUT. You’ve asked a number of questions that needed to be filled in with a lot more details and haven’t followed up. No one can answer your questions without a lot more detail.