Get_next_item is blocking. how do get a clock sampled data from driver?

UVM
, ,
1

Hi.

I’m trying to get a data from DUT which is sampled positive clock by driver as the below,

Firstly, I generate simple random data and put it into the interface in test.

always @(posedge _if.HCLK) begin
 _if.read_DATA <= $urandom;
end

and I implemented to get a generated random data which is sampled by positive clock in a driver as the below,


 task run_phase(uvm_phase phase);
   forever begin
            seq_item_port.get_next_item(req);
            $display("Received Data1 : %h", _if.read_DATA);
             @(posedge ahb_if.HCLK);
            $display("Received Data2 : %h", _if.read_DATA);
            seq_item_port.item_done(req);

        end
    endtask

After Received Data1, I get the Received Data2 but the same value. I thought that they values are must be different. the get_next_item is blocking so next data must be the next cycle’s data but it’s the same cycle’s data.

2

In reply to UVM_LOVE:

get_next_item unblocks when finish_item is called from the sequence .

Assuming that finish_item is called at Time 0 , you would observe default value of read_DATA signal in both of your displays .

You are doing a nonblocking assignment while reading it via a blocking statment , how do you expect to observe the same value ? .
One gets updated in NBA region while the display executes in active region

Driver must wait for next clock triggering before sampling signals

3

In reply to ABD_91:

In reply to UVM_LOVE:
get_next_item unblocks when finish_item is called from the sequence .
Assuming that finish_item is called at Time 0 , you would observe default value of read_DATA signal in both of your displays .
You are doing a nonblocking assignment while reading it via a blocking statment , how do you expect to observe the same value ? .
One gets updated in NBA region while the display executes in active region
Driver must wait for next clock triggering before sampling signals

Could you help me with an example code?

4

In reply to UVM_LOVE:


  bit clk ;
  
  bit [1:0] a ;
  
  initial  forever  #10 clk = !clk ;
  
  always @( posedge clk )  a <= a + 1 ;
  
  initial  begin
    
    $display(" Before posedge a is %0d " , a);
    
    @( posedge clk );
    
    $display(" After posedge a is %0d " , a);
    
     @( posedge clk );
    
    $display(" After 2nd posedge a is %0d " , a);

     $finish();
    
  end