Topics tagged DUT

Topic	Replies	Views	Activity
How to access a DUT signal from a UVM test case class? UVM UVM , hierarchical , reference , DUT	21	39669	April 11, 2023
Driving DUT internal signals with bind module UVM UVM , bind , DUT , driver , internal-signal-in-DUT , internal-signal	2	2046	October 24, 2020
Connection between DUT and TB without Interface UVM UVM , DUT , interface	3	1678	February 22, 2020
How to write structural Logic in Class SystemVerilog SystemVerilog , DUT , checker , systemverilog-Arrays-packedarrays-unpackedarrays , uvm-verilog , StructuralModelling	2	1149	July 31, 2018
VIP design UVM UVM , DUT , VIP	9	2057	July 24, 2018
Verification of dut.how to acess UVM UVM , DUT , Verification	5	1641	June 29, 2016