Dynamic sequence from command line

UVM
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1

Hi experts,

i want to use different-different sequence in one test by using command line argument. So i use this approach in base_test as below code. on that code test_seq_s will take the sequence name as string from command line. got some error while use this approch

  1. while printing the obj and seq then got null for request and response.

added snapshot.
null value for created obj and seq

  1. while i am trying to get access the sequence member then got this error for obj and seq handle.

errors for obj: ** Error (suppressible): (vlog-13276) apb_basetest.svh(38:28): Could not find field/method name (data) in ‘obj’ of ‘obj.data’.

errors for seq: ** Error (suppressible): apb_basetest.svh(39): (vopt-7063) Failed to find ‘data’ in hierarchical name ‘seq.seq.data’.

code:

    uvm_object      obj;
    uvm_factory     factory;
    uvm_sequence#(apb_pkt)    seq;

    string test_seq_s = "direct_vseq";
    void'($value$plusargs("UVM_TEST_SEQ=%0s", test_seq_s));
    factory = uvm_factory::get();
    obj = factory.create_object_by_name(test_seq_s, "", {test_seq_s,"_h"});
                
    if (obj == null) begin
      factory.print(1);
      `uvm_fatal(get_full_name(), $sformatf("could not create %0s seq", test_seq_s))
    end
    
    obj.print();
    
    if (!$cast(seq, obj)) begin
      `uvm_fatal(get_full_name(), $sformatf("cast failed - %0s is not a uvm_sequence", test_seq_s))
    end
    
    seq.print();
    $display("Obj Data: %d",obj.data);
    $display("Seq Data %d",seq.data);
2

You are getting those errors because neither uvm_object nor uvm_sequence has a member named ‘data’.

What are you trying to accomplish by printing out ‘data’?

3

Hi @cgales,

Thanks for responding,

I already added one bit type variable name as data in sequence., but the main thing is i am trying to get sequence by command line arguments (test_seq_s), based on run time sequences i will get.

4

What I suggest you do is declare a base sequence from which all the test sequences extend.

class base_seq extends uvm_sequence#(apb_pkt);
`uvm_object_utils(base_seq)
   bit data;
endclass

base_seq seq;

Then you have access to data in all the extended seqeucnes.
Another benefit is using the UVM’s existing command line switch + uvm_set_type_override=<req_type>,<override_type>)instead of doing it yourself.

1 Like
5

@dave_59

Thanks for resolution, its working as you suggested.

but i want to know that, why my approach is not working i am using “factory.create_object_by_name” . i am not identify that actual issue on that or my approach is wrong.

6

SystemVerilog rules say you cannot access members of a derived class object when referencing them from a base class variable. It has nothing to do with the approach used in the UVM to get the object constructed.