Topics tagged systemverilog-driver-monitor-virtual-interface-transaction

Topic	Replies	Views	Activity
Monitor Sampling edge UVM SystemVerilog , UVM , UVM-monitor , monitor , driver-monitor , systemverilog-uvm , systemverilog-driver-monitor-virtual-interface-transaction	1	190	January 27, 2025
What is virtual interface. why the virtual interface is used in systemverilog, what is the difference between a normal interface and a virtual interface SystemVerilog SystemVerilog , systemverilog-driver-monitor-virtual-interface-transaction , System-verilog-interface	1	631	July 27, 2023
In which phase of simulation virtual interface will assign the value of actual interface SystemVerilog SystemVerilog , systemverilog-driver-monitor-virtual-interface-transaction	1	370	July 13, 2023
VERIFICATION ASYNCHRONOUS FIFO CUMMINGS SystemVerilog SystemVerilog , fifo , sysyem-verilog , asynchronous , systemverilog-driver-monitor-virtual-interface-transaction	10	2924	February 1, 2023
Driving internal signal of DUT from uvm driver UVM UVM , force-release-behavior , systemverilog-driver-monitor-virtual-interface-transaction	1	672	August 19, 2022
Virtual interface for internal signals UVM UVM , internal-signal-in-DUT , systemverilog-driver-monitor-virtual-interface-transaction	3	2118	February 14, 2022
[SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)` SystemVerilog SystemVerilog , Clocking-Block , wait-statement , clock-synchronous , systemverilog-driver-monitor-virtual-interface-transaction	5	3508	October 1, 2021
For Dpram . how i can write a constraint block using both random write and random read signals such that write should come first and later read signal SystemVerilog SystemVerilog , systemverilog-driver-monitor-virtual-interface-transaction	5	1740	August 19, 2020

Monitor Sampling edge

SystemVerilog , UVM , UVM-monitor , monitor , driver-monitor , systemverilog-uvm , systemverilog-driver-monitor-virtual-interface-transaction

1

190

January 27, 2025

What is virtual interface. why the virtual interface is used in systemverilog, what is the difference between a normal interface and a virtual interface

SystemVerilog

SystemVerilog , systemverilog-driver-monitor-virtual-interface-transaction , System-verilog-interface

1

631

July 27, 2023

In which phase of simulation virtual interface will assign the value of actual interface

SystemVerilog

SystemVerilog , systemverilog-driver-monitor-virtual-interface-transaction

1

370

July 13, 2023

VERIFICATION ASYNCHRONOUS FIFO CUMMINGS

SystemVerilog

SystemVerilog , fifo , sysyem-verilog , asynchronous , systemverilog-driver-monitor-virtual-interface-transaction

10

2924

February 1, 2023

Driving internal signal of DUT from uvm driver

UVM

UVM , force-release-behavior , systemverilog-driver-monitor-virtual-interface-transaction

1

672

August 19, 2022

Virtual interface for internal signals

UVM

UVM , internal-signal-in-DUT , systemverilog-driver-monitor-virtual-interface-transaction

3

2118

February 14, 2022

[SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)`

SystemVerilog

SystemVerilog , Clocking-Block , wait-statement , clock-synchronous , systemverilog-driver-monitor-virtual-interface-transaction

5

3508

October 1, 2021

For Dpram . how i can write a constraint block using both random write and random read signals such that write should come first and later read signal

SystemVerilog

SystemVerilog , systemverilog-driver-monitor-virtual-interface-transaction

5

1740

August 19, 2020