Topic	Replies	Views	Activity
What is virtual interface. why the virtual interface is used in systemverilog, what is the difference between a normal interface and a virtual interface SystemVerilog SystemVerilog , systemverilog-driver-monitor-virtual-interface-transaction , System-verilog-interface	1	637	July 27, 2023
How to pass instance number in interface SystemVerilog SystemVerilog , SystemVerilog-generate-assign , System-verilog-interface	4	728	July 11, 2023
Generic components UVM UVM UVM , FIFO-UVM-VIRTUAL-INTERFACE , coverage-UVM-module-class , System-verilog-interface	5	792	June 20, 2023
Search inside module UVM/systemVerilog SystemVerilog SystemVerilog , System-verilog-interface	4	699	June 19, 2023
Error in uvm_config_db UVM UVM , System-verilog-interface	11	1029	June 13, 2023
How to redefine interface parameters [UVM PARAMETERIZED INTERFACE] UVM UVM , UVM-Parameter-virtual_interface , System-verilog-interface , uvm-parameterized_interface	1	493	May 23, 2023
Integration of a DUT with two top_level modules in a UVM SV testbench UVM UVM , uvm-testbench-verification , System-verilog-interface	12	1471	May 11, 2023
How to Connect Verilog module port to system verilog module interface port SystemVerilog SystemVerilog , System-verilog-interface	1	1106	March 15, 2023
UVM Sequence Item UVM UVM , uvm_sequence_item , sequence-item , UVM-DRIVER-INTERFACE , System-verilog-interface	5	1245	March 4, 2023
SV array of interfaces SystemVerilog SystemVerilog , System-verilog-interface	1	608	January 19, 2023

System-verilog-interface