Search inside module UVM/systemVerilog

SystemVerilog
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1

Hello,

I’m beginner on SystemVerilog, I want to know if i have the possibility to search one object if it exists inside one module ?

Thanks,

2

In reply to uvm_share:

The SystemVerilog language has no introspection. But there are tool interfaces through C API’s and tool command languages that have some search capabilities. You need to be clearer on what it is you are trying to accomplish. See https://xyproblem.info/

3

My aim is adding genericity to my verification environment, in order to will be capable to connect automaticly and with generic way the master and slave interfaces of this bridges.

For this do you have any suggestions for implementing this ?

Thanks,

4

In reply to uvm_share:

It is still not clear how you are going to achieve this. The structure of your design needs to be configured before compilation, and you can get that information and apply it to the testbench.

There are tools that can help build your testbench with templates. You may want to look at:

https://verificationacademy.com/topics/verification-methodology/uvm-framework

5

In reply to uvm_share:

Since you mentioned as beginner - I would say don’t attempt till you are really clear on your end goal/requirements. The traditional answer to your query will be VPI. Thanks to many open0-source projects, now you have the choice of Verible/Slang, etc. So you can do C++/PY/Rust etc. Again, for beginners, I wouldn’t recommend it, but this is definitely how things are evolving as I see in DV space.

Srini