How to Connect Verilog module port to system verilog module interface port

SystemVerilog
,
1

I have 2 design files one in verilog , other in system verilog with interface as port (interface has modport declaration in it)

Now i need to connect them in top …i.e verilog port to system verilog interface port …How to do that ?

##################################
module dut_v (input a,b;
              output c)

##############################
interface txf (
)
logic d,e,f;

modport tx_def (input d,e,
                output f);

modport tx_gen (output d,e,
                input f);
endinterface 
###########################
module dut_sv (input clk,
               tx.tx_def tx_if)
##############################

module top ()


endmodule
2

In reply to chaitanya kumar:

You can use hierarchical references to your interface instance. This is effectively what an interface port does as a syntax shortcut.

module top;
  txf ii();
  bit clk;

  dut_sv d1(clk, ii.tx_gen);
  dur_v  d2(ii.d,ii.e,ii.f);

endmodule

module dut_sv (input clk,
               tx.tx_gen tx_if);
endmodule

I had to switch to the tx_gen modport so the singal directions would be compatible.