How to redefine interface parameters [UVM PARAMETERIZED INTERFACE]

UVM
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1

Hello I have the following issue related to the redefinition of interface parameters.
Actually, I have a design with multiples parameters.
so basically I have an interface like this:

interface dut_if#(

parameter **MEM_NB_WORDS**           = `MEM_NB_WORDS     ,
parameter **MEM_SIZE_WORDS**         = `MEM_SIZE_WORDS   ,
parameter APB_ADDR_WIDTH         = 6      ,
  )();

// Inputs
logic                            mem_wr_clk_i ;   
logic                          mem_wr_rst_n_i ;
logic                            mem_wr_ena_i ;  
logic **[$clog2(MEM_NB_WORDS)-1:0]** mem_wr_add_i ;  
logic       **[MEM_SIZE_WORDS-1:0]** mem_wr_ben_i ;  
logic       **[MEM_SIZE_WORDS-1:0]** mem_wr_dat_i ; 

endinterface

in my regression testfile.csv I want to run each test with different parameters values , so I use PARAM_REDEFINED option (ex : PARAM_REDEFINED='MEM_NB_WORDS=32768 MEM_SIZE_WORDS=32)

But here I get an error because of port sizes mismatch, since the interace parameters did not get updated.

my question is : is there a way to redefine parameters at my interface each time I change my DUT parameters values in my testfile.csv file through param_redefine.

Thanks

2

In reply to verif_25:

Typically module and interface parameters are overridden at the place of instantiation. The two instances can be connected to the same parameters.

We do not know what tool is reading testfile.csv, and this Mentor/Siemens EDA sponsored public forum is not for discussing tool specific usage or issues. Please read your tool’s user manual or contact your tool vendor directly for support.