How to pass instance number in interface

SystemVerilog
, ,
1

HI All,

I am traying to pass interface instance in interface but getting “Illegal Operand for constant expressions” error in wait statement .


interface top_if();
  //Logics
  verif_if ve_intf[2]();
  chk_intf ck_intf[2]();

  genvar k;
  generate
    for(k=0;k < 2 ; k++) begin 
      ve_intf[k].instance_num = k;
    end
  endgenerate
endinterface 

interface verif_if ();
  //signals declaration
  int instance_num ;

  //trying to access signals of chk_intf
  initial begin 
    wait(ck_intf[instance_num].train_en[31:0] == 5); //Getting error "Illegal Operand for constant expressions [4(IEEE)]"
    $display("Training has been started");
  end 
endinterface

interface chk_intf();
  //signals declaration
  bit[31:0] train_en; //Its connected to design 
endinterface

Here,If I take single instance of chk_intf then I am not getting any error its working fine .
Hence,I need your help to fix this issue .

2

In reply to Prashant Soni:

Your code as written doesn’t compile in any of the four simulators on EDA Playground. Specifically, the arrays of verif_if and chk_intf in top_if are incorrect as they should be arrays of instances, which is not what is written.

I recommend using a parameter to verif_if to specify the instance_num instead of an int, as a parameter is a constant while a variable is not.

3

In reply to cgales:

Agreed, you can use parameters to do this.

4

Hi ,

Is there any other way to do it ? (like ref ,etc)

I will be able to do it by parameter but I will have to modify interface definition for every project and many files where I am getting this interface.

Because ,Its working fine with one instance of ck_intf interface.

Thanks,
Prashant.

5

In reply to Prashant Soni:

Interface instances are considered hardware constructs (with the exception of virtual interface handles), so you can’t use variables to index within an array of interfaces. During elaboration, the indexes need to be constant, hence why you can’t use a variable.

It works when you have a single interface since it is a constant reference.

Using a parameter will only affect the interface definition, and only in projects with this specific use case.


interface top_if();
  //Logics
  chk_intf ck_intf[2]();
 
  genvar k;
  generate
    for(k=0;k < 2 ; k++) begin : verif_intf_inst
      verif_if#(.INSTANCE_NUM(k)) ve_intf ();
    end
  endgenerate
endinterface 
 
interface verif_if ();
  parameter int INSTANCE_NUM;
 
  //trying to access signals of chk_intf
  initial begin 
    wait(ck_intf[INSTANCE_NUM].train_en[31:0] == 5); //Getting error "Illegal Operand for constant expressions [4(IEEE)]"
    $display("Training has been started");
  end 
endinterface