Is it possible to sample a signal on the same edge on which it was driven in sv?

SystemVerilog
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1

I want to sample the signal on same time stamp on which it was driven by dut. Is this possible in sv using any approach?

2

In reply to hisingh:
I show the SystemVerilog time slot regions graphically at
https://verificationacademy.com/forums/systemverilog/sampling-point-assertions

by sample the signal on same time stamp on which it was driven you mean you want the signal just before it changed, then you can do something like


always_comb @sig sig_before=$sampled(sig); 
// Function $sampled returns the sampled value of the expression for that timestep.

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
  3. Papers:
3

In reply to ben@SystemVerilog.us:

Hi Ben,
I want to sample the signal in my tb after it got changed not before.
Example:
always @(posedge clk)
value <= 1;
initial begin
@(posedge clk)
if (value)
$display(time);
end

Suppose first posedge is at 10ns.
I want the print as 10ns.
Is it possible in system verilog using clocking block or any other method?

4

In reply to hisingh:
Consider the following example, also at Edit code - EDA Playground
After the clock edge, the variable value is updated in the NBA Region. Thus, the variable being displayed in the $display is not yet updated as it has not yet change when $display function is used in the Active Region. One solution I suggest for your desired to display the changed value is to use the #1, and substract that 1ns in the readout.
Actually, I don not care for that solution (the $realtime -1ns in the $display). I would rather just use the #1 and $realtime (the 11ns in this case)


module m;
bit value, clk;
initial forever #10 clk=!clk;


  always @(posedge clk) begin
    value <= 1;
   $display("%t sampled(value) %b value %b", $realtime, $sampled(value), value); 
  end

initial begin
  @(posedge clk) 
  $display("time=%t, value=", $realtime, value);
  #1 
  if (value)
    $display("time=%t, if_value=", $realtime -1ns, value);
    $finish;
end
endmodule
//----------------
KERNEL:                   10 sampled(value) 0 value 0
# KERNEL: time=                  10, value=0
# KERNEL: time=                  10, if_value=1

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr

** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) Amazon.com
  3. Papers:
5

In reply to ben@SystemVerilog.us:

Hi, I just met the same issue. What’s your solution after then?

6

In reply to zhiyuanwang:

Use $sampled
@sig sig_before=$sampled(sig)

What is the issue? I don’t get why you are asking this question