In reply to ben@SystemVerilog.us:
Hi Ben,
I want to sample the signal in my tb after it got changed not before.
Example:
always @(posedge clk)
value <= 1;
initial begin
@(posedge clk)
if (value)
$display(time);
end
Suppose first posedge is at 10ns.
I want the print as 10ns.
Is it possible in system verilog using clocking block or any other method?