In reply to hisingh:
I show the SystemVerilog time slot regions graphically at
https://verificationacademy.com/forums/systemverilog/sampling-point-assertions
by sample the signal on same time stamp on which it was driven you mean you want the signal just before it changed, then you can do something like
always_comb @sig sig_before=$sampled(sig);
// Function $sampled returns the sampled value of the expression for that timestep.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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