Is it possible to sample a signal on the same edge on which it was driven in sv?

SystemVerilog
, ,
4

In reply to hisingh:
Consider the following example, also at Edit code - EDA Playground
After the clock edge, the variable value is updated in the NBA Region. Thus, the variable being displayed in the $display is not yet updated as it has not yet change when $display function is used in the Active Region. One solution I suggest for your desired to display the changed value is to use the #1, and substract that 1ns in the readout.
Actually, I don not care for that solution (the $realtime -1ns in the $display). I would rather just use the #1 and $realtime (the 11ns in this case)


module m;
bit value, clk;
initial forever #10 clk=!clk;


  always @(posedge clk) begin
    value <= 1;
   $display("%t sampled(value) %b value %b", $realtime, $sampled(value), value); 
  end

initial begin
  @(posedge clk) 
  $display("time=%t, value=", $realtime, value);
  #1 
  if (value)
    $display("time=%t, if_value=", $realtime -1ns, value);
    $finish;
end
endmodule
//----------------
KERNEL:                   10 sampled(value) 0 value 0
# KERNEL: time=                  10, value=0
# KERNEL: time=                  10, if_value=1

Ben Cohen
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