Issue with clocking block

SystemVerilog
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1

I am new to clocking blocks in SystemVerilog, I am facing error saying (vlog-2224) Clocking block input exec_rd_data in clocking block cb_exec is not legal. I wanted to know the mistake I did. Could anyone please help me

interface exec (input clk);
clocking cb_exec @(posedge clk);
input  exec_rd_data; 
output stall;  
endclocking 

task automatic send_inp	(input 	logic	[`DATA_WIDTH-1:0] exec_rd_data_st, output logic stall_st);
cb_exec.exec_rd_data		<= exec_rd_data_st;
cb_exec.stall	 		<= stall_st;		
endtask

endinterface
2

In reply to DurgaKundan:

A clocking block defines signals that you need to sample as inputs, or drive as outputs. It does not define the signals themselves. You need to add them the the interface. Also, the directions in your task are the opposite of what they need to be based on how you’ve defined your clocking block.

interface exec (input clk);
  logic	[`DATA_WIDTH-1:0] exec_rd_data;
  logic stall;
  clocking cb_exec @(posedge clk);
    input  exec_rd_data; 
    output stall;  
  endclocking 
 
  task automatic send_inp (output logic [`DATA_WIDTH-1:0] exec_rd_data_st,
                           input  logic stall_st);
    exec_rd_data_st = cb_exec.exec_rd_data; //needs to be blocking assignment
    cb_exec.stall  <= stall_st;		
  end task
 
endinterface

Note the assignment to exec_rd_data_st needs to be blocking, otherwise it will not have the updated value when the task returns and copies out the value.

3

In reply to dave_59:

I need to pass exec_rd_data_st as input to the task from my test bench. So when the exec_rd_data_st samples before clock edge I need to copy the value to local variable and verify the local variable against a value coming from my checker module.

how would I achieve this ?