Topics tagged SystemVerilog

Topic	Replies	Views	Activity
NO HANDLE OF VIRTUAL INTERFACE IS RECEIVED SystemVerilog SystemVerilog , virtual-interface-scoreboard-uvm	5	365	April 15, 2024
Constraint array SystemVerilog SystemVerilog , systemverilog-constraint	2	99	April 12, 2024
Function New Constructor UVM SystemVerilog , UVM	1	67	April 11, 2024
How do I avoid using #0 in an interface monitor SystemVerilog SystemVerilog , UVM	3	75	April 10, 2024
How the within syntax is working in SVA SystemVerilog SystemVerilog , assertion , SVA	7	2200	April 10, 2024
System Verilog Fine grain Process SystemVerilog SystemVerilog	2	79	April 9, 2024
Backdor access without using RAL model SystemVerilog SystemVerilog	3	73	April 8, 2024
Write a constraint for polindrome (say 32 bit)? SystemVerilog SystemVerilog , constraint	15	6324	April 7, 2024
Understanding a Bug in the Distribution Constraint SystemVerilog SystemVerilog	4	89	April 8, 2024
DUT reference model location? UVM SystemVerilog , UVM	2	74	April 7, 2024
Best Practice for Unit Tests Extending Chip-Level Tests UVM SystemVerilog , Inheritance	1	67	April 6, 2024
Solve before constraint used with implication operator SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	7	92	April 6, 2024
Checking clock period using system verilog assertion SystemVerilog SystemVerilog , assertion	30	51979	April 5, 2024
Passing variables to a subroutine on sequence match SystemVerilog SystemVerilog , assertion , SVA	2	98	April 5, 2024
LRM :: "Assertion evaluation does not wait on or receive data back from any attached subroutine" SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	1	42	April 5, 2024
Modeling dynamic delay range via subroutine SystemVerilog SystemVerilog , Modeling-dynamic-delay-range-via-subroutine	5	503	April 2, 2024
Constraint solve order SystemVerilog SystemVerilog , constraint-randomization	1	97	April 3, 2024
UVM run_test Method UVM SystemVerilog	2	63	April 3, 2024
Is there any way to set a global solve...before? SystemVerilog SystemVerilog , constraint , solve-before	1	77	April 3, 2024
Input port cannot be driven SystemVerilog SystemVerilog	8	11909	April 3, 2024
3 unique arrays - constraint SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	1	107	April 3, 2024
Manual seeding as an alternative to calling new() repeatedly SystemVerilog SystemVerilog , constraint-randomization , randomization	4	68	April 2, 2024
Local variable initialization within SVA SystemVerilog SystemVerilog , assertion , SVA , Assertion-system-verilog	1	76	April 2, 2024
Iterate through dynamic associative array, to store address-memory_data information SystemVerilog SystemVerilog	3	81	March 29, 2024
SVA: check signal remains asserted for exactly one cycle? SystemVerilog SystemVerilog , assertion	0	64	April 1, 2024
Constraint an array to have at least n pairs of consecutive x values SystemVerilog SystemVerilog , constraint-randomization , queues-systemverilog	3	429	March 31, 2024
How to build a reference model for uvm_scoreboard which perform multi-stage calculation UVM SystemVerilog	0	70	March 30, 2024
Regarding clock inheritance for sequence methods and event control SystemVerilog SystemVerilog , assertion , SVA	11	116	March 29, 2024
Evaluation of deferred assertions SystemVerilog SystemVerilog , assertion , SVA-Assertion	4	65	March 28, 2024
Submatrix Constraint Question SystemVerilog SystemVerilog , constraint-randomization	3	128	March 28, 2024