Iterate through dynamic associative array, to store address-memory_data information

SystemVerilog
1

I have an associative array within a dynamic array, to store the updated address and its corresponding data, upon any memory writes; with the index being 64-bit data and the aray_data being a 64-bit memory_data

bit [63:0] mem_alloc [ ][bit [63:0]]

Algorithm -

  1. Check If the address (key) is already present in the array if not present (memory write to the address is happening for the first time), allocate memory to mem_alloc array, and add the address as a key, and its corresponding data.

  2. If the address (key) is already present in the array, overate the array_data to the new memory_data

    for(int i=0; i<mem_alloc.size(); i++) begin
      if ( mem_alloc[i].exists(in_pkt.req_address) ) begin
        mem_alloc [i][in_pkt.req_address] = write_data;
      end else begin
        mem_alloc = new [mem_alloc.size() + 1](mem_alloc);
        mem_alloc [mem_alloc.size() - 1][in_pkt.req_address] = write_data;        
      end
    end

Currently, I am working with the above snippet, which doesn’t seem right(as in the array never gets populated).

Any idea on how I can implement the algorithm?

2

I do not understand what kind of memory structure you are trying to create. If the initial size of the dynamic array is 0, how would it ever execute the forloop body? What do you want the memory to look after the loops are finish. Please give some examples.

3

yes, i should have initialized the array with some size.

the memory structure example - { address : data }
memory_write[ ][ ] = ‘{’{0x3100630:'hf3adf3ef} , '{0x2ed3220:'hf3eff3} , '{0x31001c8:'hcaeff3} , '{0x3040:'hf0efadadbef0cade} , '{0x3100176:'hadca} , '{0x3100360:'hdca} , '{0x2d50fb1:'hbe}}

revised code-

    if (mem_alloc.size() == 0) begin
      mem_alloc = new [mem_alloc.size() + 1](mem_alloc);
      mem_alloc [mem_alloc.size() - 1][in_pkt.req_address] = write_data;
    end else begin
      for(int i=0; i<mem_alloc.size(); i++) begin
        if (mem_alloc[i].exists(in_pkt.req_address)) begin
          mem_alloc [i][in_pkt.req_address] = write_data;
        end else begin
          mem_alloc = new [mem_alloc.size() + 1](mem_alloc);
          mem_alloc [mem_alloc.size() - 1][in_pkt.req_address] = write_data;       
        end
      end
    end
4

It seems you many not understand how associative arrays work. Or maybe I don’t understand why you need two dimensions. The memory structure example you show could have been declared in a single dimension as

bit [63:0] mem_alloc [bit [63:0]] = 
   ‘{'h3100630:'hf3adf3ef , 
     'h2ed3220:'hf3eff3 , 
     'h31001c8:'hcaeff3 , 
     'h3040:'hf0efadadbef0cade,
     'h3100176:'hadca,
     'h3100360:'hdca,
     'h2d50fb1:'hbe};

All you need to do is write this line of code:

mem_alloc [in_pkt.req_address] = write_data;

SystemVerilog checks to see if that address already exists and allocates it if it does not.