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Sequential Logic Equivalence Checking

In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.

  • Formal Verification

Jin Hou

Last Updated Jul 2021
  • Clock Gating
  • Design Optimization
  • ECO
  • Equivalence Checking
  • Formal Verification
  • Low Power
  • RTL
  • Safety Mechanism
  • Sequential Analysis
  • SLEC
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  • Sequential Logic Equivalence Checking
  • 1. SLEC Introduction
  • 2. SLEC for Design Optimization
  • 3. SLEC for Bug Fix / ECO
  • 4. SLEC for Low Power Clock Gating
  • 5. SLEC for Safety Mechanism
  • Sessions

    • SLEC Introduction

      In this session, you will learn the concept of sequential logic equivalence checking (SLEC) and the common applications of SLEC.

      Track Jul 06, 2021 by Jin Hou

      • Formal Verification

    • SLEC for Design Optimization

      In this session, you will learn how to use SLEC to verify functional equivalence between two RTL designs before and after optimization.

      Track Jul 06, 2021 by Jin Hou

      • Formal Verification

    • SLEC for Bug Fix / ECO

      In this session, you will learn how to use SLEC to verify that bug fix/ ECO doesn’t introduce new bugs.

      Track Jul 06, 2021 by Jin Hou

      • Formal Verification

    • SLEC for Low Power Clock Gating

      In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.

      Track Jul 06, 2021 by Jin Hou

      • Formal Verification

    • SLEC for Safety Mechanism

      In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.

      Track Jul 06, 2021 by Jin Hou

      • Formal Verification

  • Overview

    Sequential logic equivalence checking (SLEC) is effective in finding bugs in new logic required to reduce dynamic power consumption, validating last minute ECOs, or verifying that design optimizations aren’t too aggressive. It is also very efficient in verifying safety mechanisms used in ISO 26262 and other fault mitigating designs. SLEC’s effectiveness comes from using exhaustive formal verification algorithms, which do not require a testbench; and indeed are completely automated so the user does not need to know about formal technology themselves.

    Given the formal-based nature of the analysis, SLEC can prove functional equivalence of the two designs for all inputs and all time, or identify any differences between the two designs.

    In contrast, simulation-based approaches cannot prove sequential equivalence. Indeed, even with well-written constrained-random testbenches, simulation may find functional differences depending on the quality of the testbenches but such analysis could still miss critical corner cases. As such, SLEC can save a lot of re-simulation time after small modifications of the design.

    In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.

  • Forum Discussion - Equivalence Checking

    • How to certify RTL working at last moment

      Oct 13, 2020 SystemVerilog
    • Verification Horizons Blog - Stay Updated

      Administrator1 Aug 13, 2020 Announcements
    • Could system_verilog feature "interface" apply to module development?

      Feb 13, 2020 SystemVerilog
    • News Notification: Academy Survey, Two New Courses, Verification Horizons and Formal Verification Seminar

      Administrator1 Jul 05, 2017 Announcements
    • Why do we do Equivalence Check on RTL vs Gate Netlist?

      Reuben Aug 31, 2016 SystemVerilog
    • Difference between Formal Verification through Model Checking & Assertion Based Formal Verification

      Karan Dec 20, 2015 SystemVerilog
    • Recommended UVM scoreboard architecture

      Jul 09, 2015 UVM
    • Academic division of verification approaches

      mohammed Jul 02, 2012 UVM
    Join the Equivalence Checking Discussion
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