Could system_verilog feature "interface" apply to module development?

When it comes to system_verilog interface(SV_IF) on internet, most materials describe it as a powerful tool on Test Bench.
As I know, main concept of SV_IF is used to reduce connection effort, so I instinctively use SV_IF to develop my IP.
My IP integrated many sub IPs, so SV_IF really saves a lot of connection time.
But my boss are afraid of SV_IF may run into troublesome at someone back_end tool (synthesis tool, FPGA, timing analysis tool, lint tool…).
How do you think?
If somebody have use SV_IF to complete development and MP ?
Thank you!

In reply to vatics_r89162:

We use SystemVerilog extensively in our RTL development. It’s a very powerful tool to help write concise, reusable code. Yes, most of the dialog for SystemVerilog focuses on the verification side of things. But the improvements for RTL are often understated.

Everything post-synthesis is Verilog-1995. This has been the case, well practically forever. Multi-dimensional arrays, interfaces, and other complex structures, are synthesized down to, well, just netlists, with single-dimensional portlists. So implementation tools really aren’t troubled by any of this. We’ve no trouble with STA, lint, tools etc. My only guess that one troublesome tool may be Formal Equivalence checking - we don’t currently run this. But mapping from RTL to netlist for these formal tools has always been a difficult task - even before SystemVerilog. So, not much has changed there, I believe.

My current experiences are with the Xilinx toolset, with FPGAs. However, I was using SystemVerilog for ASICs 13-14 years ago. All was well for ASICs then (FPGA tools are often many years behind ASICs - sometimes decades…)