Complexity and the need to achieve faster throughput further increases the complexity of finite state machines (FSM) of serial protocols like USB, PCIe, Ethernet, OTN, etc. These complex FSMs contain a large number of states, transition conditions, timeout mechanisms, and relevant behavior of the design in each respective state. FSMs are a source of functional bugs in any protocol. It is a very tough job to functionally verify a FSM in each of its state transition conditions and corner scenarios.
The purpose of this article is to share a strategy on how to verify any simple or complex FSM in an organized, robust, manageable, and efficient way. To verify such FSMs thoroughly we need random scenarios that cover all the possible