SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/ VALID channels.
Building a UVM  testbench is a hard job, made harder when operational RTL is not yet available to test. SystemVerilog  is a powerful modeling language that can be used to build a high level model of hardware before RTL is available. This model is fast to write, and can be as functionally complete as needed.