Accelerating Innovation: PCIe Gen7 Verification for High-Speed Designs
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks.
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Session Registration
https://event.on24.com/wcc/r/4871138/7B9DC71A0CA3942007768DC353D7771B
Date & Time
- Wednesday, March 26th
- 10:00 AM | US/Pacific
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Session Overview
With PCIe Gen 7 pushing the boundaries of data transfer speeds to 128 GT/s, alongside PAM4 signaling and advanced power management, ensuring robust and efficient design verification has become paramount.
Avery PCIe Verification IP offers a powerful, comprehensive solution for validating PCIe Gen 7 designs, while ensuring backward compatibility with earlier PCIe generations.
This session will delve into the advanced features of Avery’s PCIe Verification IP, including dynamic testbench creation, sophisticated traffic generation, error injection, and protocol compliance checks.
Discover how this native SystemVerilog/UVM VIP enables rigorous testing of performance, power efficiency, and scalability, ensuring your designs meet the demands of next-generation PCIe applications.
What You Will Learn
- Capabilities in PCIe Gen 7
- Avery Verification IP features for Gen 7 verification
Who Should Attend
- Design and Verification engineers
- Verification Managers and Directors
Products Covered
- Avery PCIe Verification IP
- Verification IQ