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83 Results

• Improving Initial RTL Quality

  Webinar - Sep 15, 2021 by Chris Giles

  This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

• Improving Initial RTL Quality

  Resource (Slides (.PDF)) - Sep 15, 2021 by Chris Giles

  This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

• Improving Initial RTL Quality | Japanese

  Resource (Japanese Translation Slides (.PDF)) - Sep 15, 2021 by Chris Giles

  This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

• Out of the Verification Crisis - Improving RTL Quality

  Article - Dec 01, 2022 by Harry Foster

  A verification crisis is upon us that will not be solved solely through improvements in verification methodologies and techniques. The solution requires a holistic and philosophical change in the way we approach design with a foundation based on bug prevention. Our proposed first step in implementing this change tightly integrates static analysis into the design process, resulting in a decrease in bug density, which has a positive impact on downstream processes and consequently reduces cost.

• Questa Design Solutions

  Topic - by Chris Giles

  Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyzes code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules.

• Integrating the Value of Questa Design Solutions in a Continuous Integration Development Flow

  Resource (Slides (.PDF)) - Feb 06, 2025 by Walter Gude

  Learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.

• ‘The Dog Ate my RTL’ Doesn’t Work Anymore

  Webinar - Feb 15, 2022 by Joe Hupcey

  In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

• ‘The Dog Ate my RTL’ Doesn’t Work Anymore

  Resource (Slides (.PDF)) - Feb 15, 2022 by Joe Hupcey

  In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

• Introduction to Questa Lint and CDC for Designers

  Webinar - Jan 25, 2022 by Mathew Yee

  In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.

• Questa Lint vs Formal AutoCheck

  Webinar - Jun 15, 2022 by Kevin Campbell

  In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.

• Questa Lint vs Formal AutoCheck

  Resource (Slides (.PDF)) - Jun 15, 2022 by Kevin Campbell

  In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.

• Accelerating RTL Simulation Techniques

  Article - Jun 06, 2015 by Lior Grinzaig - Marvell

  Long simulation run times are a bottleneck in the verification process. Coding style has a significant effect on simulation run times. Therefore, it is imperative that the code writer examine his/her code, not only by asking the question “does the code produce the desired output?” but also “is the code economical, and if not, what can be done to improve it?”

• Five Steps to Quality CDC Verification

  Resource (Paper (.PDF)) - Mar 13, 2019 by Ping Yeung

  After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules.

• Bringing Verification and Validation under One Umbrella

  Article - Feb 25, 2013 by Hans Van Der Schoot

  The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.

• Introduction to Questa Lint and CDC for Designers

  Resource (Slides (.PDF)) - Jan 25, 2022 by Mathew Yee

  In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.

• Questa Design Solutions as a Sleep Aid

  Webinar - Nov 02, 2022 by Vinayak Desai

  In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.

• Formal and the Next Normal

  Webinar - Oct 19, 2022 by Joe Hupcey

  In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.

• RTL CDC is No Longer Enough: How Gate-Level CDC is Now Essential to First Pass Success

  Article - Jun 28, 2017 by Joe Hupcey

  Clock-domain crossing (CDC) verification is a critical step in the design verification cycle. However, CDC verification is not only necessary on RTL; at 28nm nodes and below it is also essential on gate-level designs due to the possibility of the introduction of CDC errors during the synthesis phase that can lead to silicon failure. In this article we review the root cause of these challenges and introduce an automated approach to overcome these difficulties.

• No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model

  Article - Jun 01, 2016 by Rich Edelman

  SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.

• Five Steps to Quality CDC Verification

  Paper - Mar 13, 2019 by Ping Yeung

  With the number of clock domains increasing in today’s complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification.

• How Microsemi Uses Questa Formal Connectivity Check to Improve Quality and Productivity

  Article - Sep 08, 2017 by Mitchell Poplingher

  The complexity of our SoCs continues to grow at a furious pace, with a corresponding increase in the integration of more functionality using a massive number of IPs, in addition to the overlay of BIST, multiplexing of I/Os, and other "out of band" circuitry. This complexity makes manual verification of IP integration too risky, time consuming, and error prone.

• Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

  Webinar - Mar 10, 2022 by Buu Huynh

  This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.

• Exploring the Multifaceted Landscape of Formal Coverage

  Webinar - Sep 20, 2023 by Nicolae Tusinschi

  In this session, you will recognize that formal coverage serves as a barometer for design quality, pinpointing areas that require further scrutiny to achieve robustness.

• Clock-Domain Crossing

  Topic - by Chris Giles

  Designers increasingly use advanced multi-clock architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has more than one clock domain does not accurately model the silicon behavior related to the transfer of data between asynchronous clock domains. As a consequence, simulation does not accurately predict silicon functionality, risking show-stopper bug escapes due to metastability. Metastability is a phenomenon that can cause system failures in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This topic area focuses on advanced techniques to find clock-domain crossing errors before they escape into silicon.

• Unit Testing Your Way to a Reliable Testbench

  Article - Jun 06, 2015 by Neil Johnson

  Writing tests, particularly unit tests, can be a tedious chore. More tedious - not to mention frustrating - is debugging testbench code as project schedules tighten and release pressure builds. With quality being a non-negotiable aspect of hardware development, verification is a pay-me-now or pay-me-later activity that cannot be avoided.