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Find community discussions and expert answers about “rtl quality”

102 Results

Improving Initial RTL Quality

Webinar - Sep 15, 2021 Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
Improving Initial RTL Quality

Resource (Slides (.PDF)) - Sep 15, 2021 Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
Improving Initial RTL Quality | Japanese

Resource (Japanese Translation Slides (.PDF)) - Sep 15, 2021 Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.
Out of the Verification Crisis: Improving RTL Quality

Article - Dec 01, 2022 Harry Foster

A verification crisis is upon us that will not be solved solely through improvements in verification methodologies and techniques. The solution requires a holistic and philosophical change in the way we approach design with a foundation based on bug prevention. Our proposed first step in implementing this change tightly integrates static analysis into the design process, resulting in a decrease in bug density, which has a positive impact on downstream processes and consequently reduces cost.
Questa Design Solutions

Topic

Questa Design Solutions is an automated and integrated suite of verification tools for designers to improve initial RTL quality. Design Solutions analyzes code at the design stage to detect bugs early, to improve efficiency, enhance development predictability and ease pressure on schedules.
Shift Left at Scale: Siemens Factory Automation’s Journey to Consistent RTL with Questa Lint

Conference - May 12, 2026 Dominik Mentel

In this User2User Europe session, you will learn that Siemens Factory Automation successfully adopted Siemens EDA Questa Lint to strengthen RTL quality and support a modern CI/CD driven development flow. This session highlights how Questa Lint was integrated into Siemens Factory Automation’s design workflow, unexpected RTL issues uncovered, highly configurable checks and centralized rulesets enabled consistent coding practices.
Integrating the Value of Questa Design Solutions in a Continuous Integration Development Flow

Resource (Slides (.PDF)) - Feb 06, 2025 Walter Gude

Learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
‘The Dog Ate my RTL’ Doesn’t Work Anymore

Webinar - Feb 15, 2022 Joe Hupcey

In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.
‘The Dog Ate my RTL’ Doesn’t Work Anymore

Resource (Slides (.PDF)) - Feb 15, 2022 Joe Hupcey

In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.
Ensure High Quality RTL with Early Continuous Integration

Resource (Slides (.PDF)) - Feb 24, 2026 Walter Gude

Learn the value of Continuous Integration (CI) during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
Ensure High Quality RTL with Early Continuous Integration

Resource (Slides (.PDF)) - Dec 03, 2025 Walter Gude

Learn the value of Continuous Integration (CI) during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
Ensure High Quality RTL with Early Continuous Integration

Resource (Slides (.PDF)) - Jun 05, 2025 Walter Gude

Learn the value of Continuous Integration (CI) during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
Ensure High Quality RTL with Early Continuous Integration

Resource (Slides (.PDF)) - Jun 03, 2025 Walter Gude

Learn the value of Continuous Integration (CI) during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
Verification Academy Live: El Segundo

Seminar - Feb 24, 2026 Joe Hupcey

This seminar explores technologies and techniques you can adopt to increase your verification productivity. We will cover: How the new AI/ML paradigm shift across the industry is enabling functional verification productivity gains Benefits of an automated Continuous Integration flow to enhance RTL quality and streamline development processes Protecting against data corruption with formal security verification Latest advancements in RTL simulation
Verification Academy Live: El Segundo

Seminar - Feb 06, 2025 Joe Hupcey

This seminar will update you on technologies and techniques you can adopt to increase your verification productivity today. Specifically, we will cover: How the AI/ML paradigm shift enables functional verification productivity gains The benefits of an automated CI flow to enhance RTL quality and streamline development processes How to protect against data corruption with formal security verification Advancements in RTL simulation
Introduction to Questa Lint and CDC for Designers

Webinar - Jan 25, 2022 Mathew Yee

In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.
Questa Lint vs Formal AutoCheck

Webinar - Jun 15, 2022 Kevin Campbell

In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.
Questa Lint vs Formal AutoCheck

Resource (Slides (.PDF)) - Jun 15, 2022 Kevin Campbell

In this session, you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.
Accelerating RTL Simulation Techniques

Article - Jun 06, 2015 Lior Grinzaig - Marvell

Long simulation run times are a bottleneck in the verification process. Coding style has a significant effect on simulation run times. Therefore, it is imperative that the code writer examine his/her code, not only by asking the question “does the code produce the desired output?” but also “is the code economical, and if not, what can be done to improve it?”
Agentic AI for RTL Signoff: Gen AI for Chip Design Flows using Questa Toolkit

Conference - Mar 05, 2026 Ronen Shoham

This tutorial will detail the architectural principles behind an Agentic AI approach, demonstrating how MCP facilitates interoperability and enables autonomous, trusted RTL signoff. Attendees will gain insights into fostering design quality and liberating engineers from repetitive tasks.
Five Steps to Quality CDC Verification

Resource (Paper (.PDF)) - Mar 13, 2019 Ping Yeung

After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules.
Enabling Formal Verification at Scale: An Agentic AI-driven Approach to RTL Bring-up

Conference - Apr 28, 2026 Nirmala Balakrishnan

This session describes a verification methodology transformation that enabled a design team to adopt formal verification techniques despite being completely new to formal flows. The team previously relied heavily on simulation-based verification without static analysis or formal methods, with limited personnel and expertise to write properties or deploy formal tools effectively.
Bringing Verification and Validation under One Umbrella

Article - Feb 25, 2013 Hans Van Der Schoot

The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.
Introduction to Questa Lint and CDC for Designers

Resource (Slides (.PDF)) - Jan 25, 2022 Mathew Yee

In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.
Full Spectrum Equivalence Checking: From C++ to the FPGA Bitstream

Webinar - Jul 22, 2026 Kevin Urish

In this session, we will equip you with comprehensive solutions to tackle current and emerging verification trends and compliance requirements for FPGA designs including optimizing verification productivity and quality and streamlining your high-level language verification flow for FPGA designs.