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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

      • Introduction to UVM
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      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
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    • Pattern Resources

      • Start Here - Patterns Library Overview
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
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      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
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      • UVM Connect - SV-SystemC interoperability
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    • Coding Guidelines & Deployment

      • Code Examples
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    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
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      • Bus Protocol Coverage
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      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Featured & On-Demand

      • Continuous Integration - March 28th
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      • The Dog ate my RTL
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    • Conferences & WRG

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    • Siemens EDA Learning Center

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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Home
  • Static-Based Techniques
  • Improving RTL Quality

Improving RTL Quality

RTL quality issues continue to impact development projects. These are often found late in the project when they are most expensive to find and fix. A static and formal flow focused on improving RTL quality automates verification for the designer and improves verification efficiency, resulting in more predictable development at a lower cost.

Chris Giles
Mark Eslinger
Kurt Takara
Atul Sharma
Mathew Yee
Kevin Campbell
Buu Huynh
Static-Based Techniques
Walk

Featured On-Demand Sessions

Questa Lint vs Formal AutoCheck

Questa Lint vs Formal AutoCheck Session | Kevin Campbell - Subject Matter Expert

In this session you will gain an understanding of the similarities and differences between Lint and Formal AutoChecking tools, and how they can be used together to increase the quality of RTL deliverables.

Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

Fix an FPGA: Ways to Find and Fix FPGA Failures Faster | Subject Matter Expert - Buu Huynh | Siemens EDA Functional Verification Webinar Series

This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.

‘The Dog Ate my RTL’ Doesn’t Work Anymore

DAC 2021 | ‘The Dog Ate my RTL’ Doesn’t Work Anymore

In this session, you will learn how to identify ways to remove the lack of a testbench as the cause of lower quality RTL and how to accomplish an improved RTL quality-focused flow.

Introduction to Questa Lint and CDC for Designers

Introduction to Questa Lint and CDC for Designers | Subject Matter Expert - Mathew Yee | Siemens EDA 2022 Functional Verification Webinar Series

In this session, you will learn why code quality matters regardless of whether you are coding an ASIC, FPGA or IP block, what metastability is and how it will affect silicon bring-up and how addressing these points during the design process is critical to achieving tight schedules with limited resources.

Improving Initial RTL Quality

Improving Initial RTL Quality Session | Subject Matter Expert - Chris Giles

This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

Questa Design Solutions Demos

Questa® Lint Demo - Find and Fix RTL Issues

Questa Lint Demo Session | Subject Matter Expert - Tom Carlstedt-Duke

This session demonstrates how Questa Lint is used to find and fix RTL issues without a testbench or constraints

Questa® AutoCheck Demo - Advanced Linting

Questa AutoCheck Demo - Advanced Linting Session | Subject Matter Expert - Mark Eslinger

This session demonstrates the Questa AutoCheck advanced linting tool and how it can be used with Questa Lint and Questa X-Check for a full suite of RTL checks without a testbench.

Questa® X-Check Demo - Identify "X" Issues

Questa X-Check Demo - Identify "X" Issues Session | Subject Matter Expert - Mark Eslinger

This session demonstrates how the Questa X-Check tool can identify X issues without any simulation, complementing Questa Lint and AutoCheck for a full suite of RTL checks.

Questa® CDC Verification Demo

Questa CDC Verification Demo Session | Subject Matter Expert - Kurt Takara | Clock-Domain Crossing Verification (CDC) Course

This session demonstrates the Questa CDC Verification comprehensive solution to clock-domain verification.

Questa® Reset Domain Crossing (RDC) Demo

Questa® Reset Domain Crossing (RDC) Demo Session | Subject Matter Expert - Atul Sharma

This session will demonstrate the Questa RDC Verification Solution and will introduce key features in RDC GUI, like RDC Matrix, Directive Window and other debug features.

News

Semiconductor Engineering Articles:

  • Do You Know For Sure Your RISC-V RTL Doesn’t Contain Any Surprises?

  • Debug Solutions For Designers Accelerate Time To Verification

EE Times Article:

  • Out of the Verification Crisis: Improving RTL Quality


Verification Horizons Blogs

Non-stick surfaces and RTL design

By Chris Giles • November 15, 2021

Reaching into the part of my brain where the memories are still on paper, stuck in file drawers in metal filing cabinets, covered with dust, indexed by cryptic number/letter combinations that pretty much ensure I have almost no recall, I find a memory of a former colleague who referred to himself as “non-stick surface man”. (Actually he referred to himself with a trademark but I don’t want to get him into trouble so – let’s just non-stick with Non-Stick Surface Man, or Mr. NSSM for short.) He called himself this because it was his design goal that his code be perfect when he brought it to be integrated into the broader design and tested. It was a badge of honor he held over the rest of us heathens who dared bring a bug to the party. Of course, you can imagine that the rest of us on the team were overjoyed (well, that might be a bit much – let’s just say “happy”) when a bug actually turned out to be in his code. There were lots of false alarms, moments of panic in his eyes that he missed something, followed by louder and louder self-proclamation of his Mr. NSSM status when proven innocent. Ultimately, bugs did happen in his code – but in fairness – there weren’t many.

Read the entire blog post >


Design Linting for ISO 26262

By Jake Wiltgen • September 20, 2021

ISO 26262 remains the state of the art standard guiding the development of electronic and electronic systems destined for the automobile. By 2030, some estimate that the BOM of a vehicle will be 50% electronics and electronic components. Regardless, ISO 26262 has solidified itself as the backbone of the safety lifecycle for semiconductor companies. The standard is far reaching, delivering guidance from concept to decommission across OEMs, Systems Integrators and Suppliers. For suppliers, the guidance is focused into three areas:

  • Lifecycle Management: The process and governance required within the lifecycle
  • Systematic Failures: The activities and work products required to ensure the component operates per the requirements
  • Random Failures: The activities and work products required to ensure the component fails safely when a random failure occurs

Read the entire blog post >


Leave the House With a Clean Design

By Chris Giles • September 14, 2021

Several years ago, I posted a job opening for a Design Engineer. To my surprise, a few of the responses I received were from individuals in the fashion industry, looking for a fashion design position. Apparently, I didn’t write the job description well enough. Actually, on second thought, I think I did but those fashion types who applied probably assumed that I mistakenly listed the job as microprocessor design and that the job really was about designing pants. But I digress. Design is admittedly a very vague word. It means a lot of things to a lot of people. So, let me be perfectly clear – in the context of the rest of this entry, when I say design, I mean digital hardware design. Clear?

Read the entire blog post >

Japanese Translation

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