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Slave Sequences (Responders)

Chapter - Mar 31, 2014 by Verification Methodology Team

A slave sequence is used with a driver that responds to events on an interface rather than initiating them. This type of functionality is usually referred to as a responder.
Wait for a Signal

Chapter - Mar 31, 2014 by Verification Methodology Team

In the general case, synchronizing to hardware events is taken care of in UVM testbenches by drivers (proxy & BFM) and monitors (proxy & BFM).
Interrupt Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

In hardware terms, an Interrupt is an event which triggers a new thread of processing.
Virtual Sequencers (Not Recommended)

Chapter - Mar 31, 2014 by Verification Methodology Team

A virtual sequence is a sequence which controls a stimulus generation process using several sequencers.
Command Line Processor

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM command line processor is used to interact with plusargs. Several plusargs are pre-defined and part of the UVM standard.
Transaction Methods

Chapter - Mar 31, 2014 by Verification Methodology Team

When working with data object classes derived from uvm_objects, including ones derived from uvm_transactions, uvm_sequence_items and uvm_sequences, there are a number of methods which are defined for common operations on the data objects properties.
End of Test

Chapter - Mar 31, 2014 by Verification Methodology Team

A UVM testbench, if is using the standard phasing, has a number of zero time phases to build and connect the testbench, then a number of time consuming phases, and finally a number of zero time cleanup phases.
UVM Driver

Chapter - Mar 30, 2014 by Verification Methodology Team

The UVM driver is responsible for communicating at the transaction level with the sequence via TLM communication with the sequencer and converting between the sequence_item on the transaction side and pin-level activity in communicating with the DUT via a virtual interface.
UVM Monitor

Chapter - Mar 30, 2014 by Verification Methodology Team

The first task of the analysis portion of the testbench is to monitor activity on the DUT. A Monitor, like a Driver, is a constituent of an agent.
UVM Factory

Chapter - Mar 27, 2014 by Verification Methodology Team

The purpose of the UVM factory is to enable an object of one type to be substituted with an object of a derived type without changing the testbench structure or even the testbench code.
Post-Run Phases

Chapter - Mar 27, 2014 by Verification Methodology Team

Many analysis components perform their analysis on an ongoing basis during the simulation run.
Backdoor Accesses

Chapter - Mar 27, 2014 by Verification Methodology Team

The UVM register model facilitates access to hardware registers in the DUT either through front door accesses or back door accesses.
Package Organization

Chapter - Mar 27, 2014 by Verification Methodology Team

UVM organizes all of its base classes into a SystemVerilog Package.
UVM Verification Component

Chapter - Mar 27, 2014 by Verification Methodology Team

A UVC ( U VM V erification C omponent) is a Verification Component designed for use in UVM. It is a multi-faceted definition and has different layers of meaning in different contexts.
UVM Connect

Chapter - Mar 26, 2014 by Adam Erickson

Learn about how to use UVM Connect to link UVM and SystemC using TLM.
UVMC Connections

Chapter - Mar 26, 2014 by Adam Erickson

To communicate, verification components must agree on the data they are exchanging and the interface used to exchange that data.
UVMC Conversion

Chapter - Mar 26, 2014 by Adam Erickson

Object transfer requires converters to translate between the two types when crossing the SC-SV language boundary.
UVMC Command API

Chapter - Mar 26, 2014 by Adam Erickson

The UVM Connect Command API gives SystemC users access to key UVM features in SystemVerilog.
Questa Verification IP, More than just a BFM

Webinar - Feb 12, 2014 by Tom Fitzpatrick

Today’s advanced UVM environments require more than a standard BFM to support environment reuse, randomized stimulus, generation of traffic scenarios, coverage collection, etc.
UART Example (.tgz)

Resource (Tarball) - Dec 04, 2013 by Verification Methodology Team

Most of the functional coverage can be derived from content of the registers which are used to control and monitor the behavior of the device. The register interface may also serve the data path. There may be scope for using assertions on signal interfaces.
Specification to Test Plan

Chapter - Dec 04, 2013 by Harry Foster

The goal in creating a coverage model spreadsheet or testplan is to capture a subset of the design intent and behavior that is targeted for functional coverage.
UART Example Test Plan

Chapter - Dec 04, 2013 by Harry Foster

As part of the verification planning process, a test plan should be drawn up to list all the design features to be tested and to help identify the type of functional coverage required to check that all the tests have been run for all conditions.
Executable Test Plan Format

Chapter - Dec 04, 2013 by Harry Foster

A testplan is a document which captures the important features of a design and how they will be verified.
Cookbook Code Examples

Chapter - Dec 04, 2013 by Verification Methodology Team

The UVM Cookbook has a number of UVM code examples which are designed to help illustrate the various topics discussed. The link to each example also appears on the appropriate cookbook page.
UART Reference

Resource (Reference Documentation) - Dec 04, 2013 by Verification Methodology Team

The Siemens EDA UART is a soft design IP core. It has been designed to be generally compatible with the industry standard 16550A UART, but there are a small number of differences.