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Metric Analyzers

Chapter - Mar 31, 2014 by Verification Methodology Team

Metric Analyzers watch and record non-functional behavior such as latency, power utilization, and other performance-related measurements.
Objections

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM_objection class provides a means for sharing a counter between participating components and sequences.
Separate Top-Level Modules

Chapter - Mar 31, 2014 by Verification Methodology Team

Co-emulation is done by running two distinct synchronized model evaluations - one on a hardware emulator, and one on a software simulator.
Split Transactors

Chapter - Mar 31, 2014 by Verification Methodology Team

Driver and monitor transactors contain a mixture of transaction-level code to communicate with the testbench, and clock-driven HDL signal accessing code to communicate with the DUT through a virtual interface.
Back Pointers

Chapter - Mar 31, 2014 by Verification Methodology Team

In the original single top bidirectional driver example, all driver activity is initiated from the testbench domain.
Defining an API

Chapter - Mar 31, 2014 by Verification Methodology Team

As the timed portion of the traditional UVM transactor must be moved over to the HDL domain.
Emulation-Ready Testbench Examples

Chapter - Mar 31, 2014 by Verification Methodology Team

This article steps through the process of converting a comprehensive traditional single top UVM example testbench to an equivalent one with a dual domain partitioned structure that is ready for co-emulation with Veloce.
Sequence Priority

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM sequence use model allows multiple sequences to access a driver concurrently.
Overriding Sequences and Sequence Items

Chapter - Mar 31, 2014 by Verification Methodology Team

Sometimes, during stimulus generation, it is useful to change the behavior of sequences or sequence items.
Layering Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

Many protocols have a hierarchical definition - for example, PCI express, USB 3.0, and MIPI LLI all have a Transaction Layer, a Transport Layer, and a Physical Layer.
Locking or Grabbing a Sequencer

Chapter - Mar 31, 2014 by Verification Methodology Team

There are a number of modeling scenarios where one sequence needs to have exclusive access to a driver via a sequencer.
Hierarchical Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

When dealing with sequences, it helps to think in layers when considering the different functions that a testbench will be asked to perform.
Portable VHDL Testbench Automation with Intelligent Testbench Automation

Article - Mar 31, 2014 by Matthew Ballance

We've come a long way since digital designs were sketched as schematics by hand on paper and tested in the lab by wiring together discrete integrated circuits, applying generated signals and checking for proper behavior. Design evolved to gate-level on a workstation and on to RTL, while verification evolved from simple directed tests to directed random, constrained-random, and systematic testing
Register-Level Stimulus

Chapter - Mar 31, 2014 by Verification Methodology Team

Stimulus that accesses memory mapped registers should be made as abstract as possible.
Register Model & Structure

Chapter - Mar 31, 2014 by Verification Methodology Team

In order to be able to use the UVM register model effectively, it is important to have a mental model of how it is structured in order to be able to find your way around it.
Register Sequence Examples

Chapter - Mar 31, 2014 by Verification Methodology Team

To illustrate how the different register model access methods can be used from sequences to generate stimulus, this page contains a number of example sequences developed for stimulating the SPI master controller DUT.
Generating Register Models

Chapter - Mar 31, 2014 by Verification Methodology Team

A register model can be written by hand, following the pattern given for the SPI master example.
Integrating a UVM Register Model in a Testbench - Implementation

Chapter - Mar 31, 2014 by Verification Methodology Team

The integration process for the register model involves constructing it and placing handles to it inside the relevant configuration objects, and then creating the adaption layers.
Memory-Level Stimulus

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model also supports memory access. Memory regions within a DUT are represented by memory models which have a configured width and range and are placed at an offset defined in a register map
"Quirky" Registers

Chapter - Mar 31, 2014 by Verification Methodology Team

Quirky registers are just like any other register described using the register base class except for one thing.
Integrating a UVM Register Model in a Testbench - Overview

Chapter - Mar 31, 2014 by Verification Methodology Team

Within an UVM testbench a register model is used either as a means of looking up a mirror of the current DUT hardware state or as means of accessing the hardware via the front or back door and updating the register model database.
Register Model Coverage

Chapter - Mar 31, 2014 by Verification Methodology Team

Which covergroups get built within a register block object or a register object is determined by a local variable called m_has_cover.
The Sequence Library

Chapter - Mar 31, 2014 by Verification Methodology Team

UVM provides a class for randomly creating and running sequences. This class is called uvm_sequence_library.
Stopping a Sequence

Chapter - Mar 31, 2014 by Verification Methodology Team

Once started, sequences should not be stopped.
Virtual Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

A virtual sequence is a sequence which controls stimulus generation using several sequencers.