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An Enhanced UPF Example
Session - May 31, 2013 by Chuck Seeley
This session presents an extended example illustrating the usage of the UPF 2.0 features of IEEE Std 1801 UPF for specification of the power management architecture for a simple design.
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Using Supply Sets
Session - Apr 29, 2013 by Chuck Seeley
This session presents the UPF 2.0 concept of a “supply set” and the related commands and options used for defining and using supply sets.
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UPF 2.0 Enhancements
Session - Apr 08, 2013 by Chuck Seeley
This session presents UPF 2.0 commands and options that improve usability and provide greater flexibility.
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A Simple UPF Example
Session - Apr 08, 2013 by Chuck Seeley
This session presents an extended example illustrating the usage of the UPF 1.0 subset.
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Getting Started with UPF
Session - Apr 08, 2013 by Erich Marschner
This session presents the core commands and options in UPF 1.0 subset.
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Introduction to Power Aware Verification
Session - Apr 08, 2013 by Erich Marschner
This session introduces the IEEE Std 1801 Unified Power Format (UPF).
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Overview of UPF
Session - Apr 08, 2013 by Erich Marschner
This session gives a quick, high-level overview of the evolution of the UPF standard.
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Power Aware Verification
Track - Apr 05, 2013 by Erich Marschner
This track introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.
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Functional Verification Study - 2012
Session - Apr 01, 2013 by Harry Foster
In this session, Harry Foster highlights the key findings from the 2012 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.
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UVM 1.1d Class Reference
Resource (Reference Documentation) - Mar 07, 2013 by
v1.1d The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
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Bringing Verification and Validation under One Umbrella
Article - Feb 22, 2013 by Hans Van Der Schoot
The standard practice of developing RTL verification and validation platforms as separate flows, forgoes large opportunities to improve productivity and quality that could be gained through the sharing of modules and methods between the two. Bringing these two flows together would save an immense amount of duplicate effort and time while reducing the introduction of errors, because less code needs to be developed and maintained.
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System Level Code Coverage using Vista Architect and SystemC
Article - Feb 22, 2013 by Ken P. McCarty - Siemens EDA
SoC are constantly becoming more and more complex forcing design teams to eke out as much performance as possible just to stay competitive. Design teams need to get it right from the start and can't wait until it's built to find out how it truly performs. This is where System Level Modeling and SystemC/TLM shine.
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The Evolution of UPF: What’s Next?
Article - Feb 22, 2013 by Erich Marschner
Usage of the Unified Power Format (UPF) is growing rapidly as low power design and verification becomes increasingly necessary. In parallel, the UPF standard has continued to evolve. A previous article1 described and compared the initial UPF standard, defined by Accellera, and the more recent IEEE 1801-2009 UPF standard, also known as UPF 2.0. The IEEE definition of UPF is the current version of the standard, at least for now, but that is about to change.
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Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
Article - Feb 22, 2013 by Ajeetha Kumari, Srinivasan Venkataramanan - CVC Pvt. Ltd.
SystemVerilog has become the most widely deployed Verification language over the last several years. Starting with the early Accellera release of 3.1a standard, the first IEEE 1800-2005 standard fueled the widespread adoption in tools and user base. Since 2005 there is no look-back to this "all encompassing" standard that tries to satisfy and do more for RTL Designers and Verification engineers alike.
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SVA in a UVM Class-based Environment
Article - Feb 22, 2013 by Ben Cohen
This article demonstrates how SVA complements a UVM class-based environment. It also demonstrates how the UVM severity levels can be used in all SVA action blocks instead of the SystemVerilog native severity levels.
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The Formal Verification of Design Constraints
Article - Feb 22, 2013 by Ajay Daga - FishTail Design Automation
There are two approaches to the verification of design constraints: formal verification and structural analysis. Structural analysis refers to the type of analysis performed by a static timing tool where timing paths either exist or not based on constant settings and constant propagation.
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OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale”
Article - Feb 22, 2013 by Mark Litterick, Verilab GmbH
While it is generally accepted that the Universal Verification Methodology (UVM) is the way forward for modern SystemVerilog based verification environments, many companies have an extensive legacy of verification components and environments based on the predecessor, the Open Verification Methodology (OVM).
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Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
Resource (Technical Paper) - Feb 07, 2013 by Rich Edelman
In a verification environment the task of a monitor is to monitor activity on a set of DUT pins. This could be as simple as looking at READ/WRITE pins or as complex as a complete protocol bus, such as AXI or PCIe. In a very simple case a monitor can be looking at a pin or a set of pins and generating an event or raising a flag every time there is a change in signal values. The flag or event can trigger a scoreboard or coverage collector to perform an activity.
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Monitors, Monitors Everywhere – Who Is Monitoring the Monitors
Paper - Feb 07, 2013 by Rich Edelman
This paper will review phase-level monitoring, transaction-level monitoring, and general monitoring. In-order and out-of-order transaction-level monitors and UVM constructs for single and multiple port monitors will be demonstrated, including discussion about simple function implementations versus FIFO and threaded implementations. A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated.
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Verification Horizons - Volume 9, Issue 1
Resource (Verification Horizons Archive) - Feb 01, 2013 by Tom Fitzpatrick
"As verification engineers, we have to be able to forecast the accurate completion of our projects and also be able to cope with problems that may occur. Unfortunately, there are severe consequences when we get it wrong.”
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Improve AMS Verification Quality
Session - Jan 25, 2013 by Ahmed Eisawy
This session introduces a tool can be adapted in existing design flows supporting the available methodologies with little or no impact on the design flow.
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Extend Structured Formal Verification to AMS
Session - Jan 25, 2013 by Ahmed Eisawy
This sessions defines the necessary extensions to the Digital Structured Formal Verification to the Mixed-Signal environment.
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Extend Power-Aware Verification to AMS
Session - Jan 25, 2013 by Ahmed Eisawy
This session introduces the concept of Power-Aware verification, why it’s needed in a Digital domain and how it can be used in an AMS design.
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Analog Aspects in AMS
Session - Jan 25, 2013 by Ahmed Eisawy
This session covers the main aspects that affect the Quality of an Analog design and introduces the possible means to address those areas.
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Overview to Improve AMS Quality
Session - Jan 25, 2013 by Ahmed Eisawy
This session introduces the challenges in improving Mixed-Signal Verification Quality.