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1772 Results

  • AMS Modeling Guidance

    This session attempts to offer some general guidelines in developing Models for the various Analog and Mixed-Signal domain.

  • Modeling Abstraction

    This session defines the language choices available in a Mixed-Signal design structure and how each choice impacts the performance and quality of the results.

  • AMS Engines

    This session covers the 2 main simulator technologies used in Mixed-Signal verification: AMS Simulation and Analog/Digital Co-Simulation.

  • Overview to Improve AMS Performance

    This session introduces the challenges in Mixed-Signal verification performance.

  • VHDL-2008 Overview

    This session is a brief overview of all the VHDL-2008 improvements.

  • Testbench Enhancements

    This session examines testbench enhancements and the value they deliver.

  • RTL Enhancements

    This session examines the RTL enhancements in VHDL-2008 and the value they deliver.

  • Operator Enhancements

    This session will discuss the value of the many new enhancements to the VHDL-2008 operators.

  • Package Type Enhancements

    The session explores the new packages and modifications to the packages as well as the value these updates deliver.

  • Fixed Point Package

    This session will explain the details of the new fixed point package.

  • Floating Point Package

    This session will explain the details of the new floating point package.

  • VHDL-2008 Why It Matters

    VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.

  • Effectively Modeling and Analyzing Coverage

    In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.

  • UVM 1.1c Class Reference

    v1.1c The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.

  • More UVM Registers

    In this session, you will learn how to implement registers and score-boarding at the register layer.

  • Protocol Layering

    In this session, you will learn how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.

  • Introduction to UVM Registers

    In this session, you will be introduced to the Register Layer and how to get started writing tests and sequences and checking results at the register layer.

  • C-Based Stimulus for UVM

    In this session, you will learn more about a technique in which C stimulus can be applied to the DUT via an existing UVM testbench that contains one or more bus agents.

  • UVM Debug

    In this Verification Cookbook session, you will learn how to maximize your ability debug your testbench so you can get on with the real task of verifying your design.

  • Scoreboards and Results Predictors in UVM

    In this session, you will learn how to outline the proper architecture of scoreboards and predictors in UVM and how they relate to coverage.

  • OVM to UVM Migration

    In this session you will be introduced to a step-by-step discussion of how to migrate your OVM code to UVM, including running the transition script, known differences between OVM and UVM and additional steps to take advantage of the new features offered in UVM.

  • Customization in UVM

    In this session, you will learn how to set up configuration objects for your environment and verification components, including setting virtual interfaces to connect to your DUT and how to use packages to organize parameters and other configuration information to allow an efficient compilation strategy while maximizing flexibility.

  • Improving FPGA Debugging with Assertions

    Here’s one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics.

  • UVM Connect 2.2 Kit

  • FPGA Verification Capabilities

    This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.