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Hardware Emulation: Three Decades of Evolution

Article - Mar 11, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

About 30 years ago, when computers revolutionized the semiconductor design process, a new verification technology appeared on the horizon under the name of hardware emulation. It was implemented in a big-box and billed as being able to verify and debug chip designs.
Evolving the Use of Formal Model Checking in SoC Design Verification

Article - Mar 11, 2015 by Ram Narayan

Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.
Small, Maintainable Tests

Article - Mar 11, 2015 by Ashley Winn - Sondrel IC Design Services

In any verification environment it takes a significant amount of work to keep all the tests running and to ensure that each test continues to be effective. To make this job easier, tests need to be kept as short as possible and should be written at the highest level of abstraction possible for the feature being tested.
Functional Coverage Development Tips: Do’s and Don'ts

Article - Mar 11, 2015 by Samrat Patel, Vipul Patel - eInfochips

The fundamental goal of a verification engineer is to ensure that the Device Under Test (DUT) behaves correctly in its verification environment. As chip designs grow larger and more complex with thousands of possible states and transitions, a comprehensive verification environment must be created that minimizes development effort.
UVM Connect 2.3.0 Kit

Resource (Tarball) - Mar 10, 2015 by John Stickley
UVM Connect 2.3.0 Primer

Resource (Reference Documentation) - Mar 10, 2015 by John Stickley
Coverage Data Exchange Is No Robbery…Or Is It?

Resource (Paper (.PDF)) - Mar 03, 2015 by Darron May

Coverage is extremely important to the modern verification flow. Most vendors have already figured that unifying data across all verification engines leads to a more efficient and integrated environment. There are many challenges to be solved unifying and sharing data across a single vendor’s tool set which are further complicated when wanting to share data across multiple vendors’ tool sets.
Coverage Data Exchange Is No Robbery…Or Is It?

Resource (Poster Paper) - Mar 03, 2015 by Darron May

In this poster paper, presented at DVCon 2015, you learn more that the Unified Coverage Database was architected in 2005 to unify coverage collection across all verification engines, UCDB was first released within Questa and ModelSim in early 2006 as a way of natively storing, analyzing and reporting on functional coverage, code coverage and assertions.
Coverage Data Exchange Is No Robbery…Or Is It?

Paper - Mar 03, 2015 by Darron May

Over the last few years all the major vendors have realized that unifying the way coverage is stored in a common database allows the results of multiple verification tools to be combined and for these tools to share the data to improve coverage closure. Simulation, Emulation and Formal engines should all be using the same database to provide the user with the complete picture, and allow the analysis of all data in a common way.
UVM Connect 2.3 Kit

Resource (Tarball) - Feb 18, 2015 by John Stickley
Coverage Cookbook - Japanese Release

Resource (Cookbook Japanese Translation) - Jan 14, 2015 by
Dealing With UVM and OVM Sequences

Article - Dec 29, 2014 by Verification Horizons
Don't Forget the Little Things That Can Make Verification Easier

Article - Dec 29, 2014 by Verification Horizons
Introduction to Questa X-Check

Webinar - Dec 20, 2014 by Doug Smith

In this session, you will learn how Questa X-Check finds sources of X in your design and identifies issues where X is propagated and corrupts properly initialized registers.
Cache Coherent Interface Verification IP

Article - Dec 17, 2014 by Verification Horizons
Power Aware Verification in Mixed-Signal Simulation

Resource (Paper (.PDF)) - Dec 10, 2014 by

Power efficiency is a very important metric in designing mobile and other industrial SoCs. Various power saving techniques are used to reduce power consumption. To verify the power distribution network and power state transitions in SoC designs, power-aware verification is performed with the power architecture described in UPF. Many of those SoCs are mixed-signal in nature and have power-regulation functionality on the chip.
Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide

Article - Nov 20, 2014 by Verification Horizons
Hey You, Design Engineer!

Article - Nov 20, 2014 by Verification Horizons

Hey you, verification engineer. Yeah, you. Are you tired of how long it takes you to figure out what the design is supposed to do? How much time it takes to jury-rig up all the pieces of the verification environment only to be told that isn’t what is supposed to be tested in the first place? Well, this article is for you.
Using Mentor Questa® for Pre-silicon Validation of IEEE 1149.1-2013 based Silicon Instruments

Article - Nov 19, 2014 by Verification Horizons
Introduction to Questa CDC

Webinar - Nov 12, 2014 by Doug Smith

In this session, you will learn how the Questa Clock-Domain Crossing (CDC) solution focuses on the interaction between these clock-domains.
Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs

Article - Nov 11, 2014 by Verification Horizons
Questa Coverage Closure

Demo - Oct 22, 2014 by Thomas Ellis

In this demo, you will learn a few of the key features of the Questa Verification Platform as applies to the process of coverage closure.
Introduction to Questa CoverCheck

Webinar - Oct 16, 2014 by Doug Smith

In this session, you will learn how Questa CoverCheck automates and accelerates the process of code coverage closure.
Establishing a Company Wide Verification Reuse Library

Webinar - Oct 15, 2014 by Bob Oden

In this session, you will learn how to outline key characteristics of a reuse verification library and will outline a proven reuse methodology.
Navigating the Perfect Storm: New School Verification Solutions

Webinar - Oct 15, 2014 by Tom Fitzpatrick

This session introduces today’s trends and challenges in SoC design and verification and outlines a path for navigating this “perfect storm."

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Article - Mar 11, 2015 by Dr. Lauro Rizzatti - Rizzatti LLC

Article - Mar 11, 2015 by Ram Narayan

Article - Mar 11, 2015 by Ashley Winn - Sondrel IC Design Services

Article - Mar 11, 2015 by Samrat Patel, Vipul Patel - eInfochips

Resource (Tarball) - Mar 10, 2015 by John Stickley

Resource (Reference Documentation) - Mar 10, 2015 by John Stickley

Resource (Paper (.PDF)) - Mar 03, 2015 by Darron May

Resource (Poster Paper) - Mar 03, 2015 by Darron May

Paper - Mar 03, 2015 by Darron May

Resource (Tarball) - Feb 18, 2015 by John Stickley

Resource (Cookbook Japanese Translation) - Jan 14, 2015 by

Article - Dec 29, 2014 by Verification Horizons

Article - Dec 29, 2014 by Verification Horizons

Webinar - Dec 20, 2014 by Doug Smith

Article - Dec 17, 2014 by Verification Horizons

Resource (Paper (.PDF)) - Dec 10, 2014 by

Article - Nov 20, 2014 by Verification Horizons

Article - Nov 20, 2014 by Verification Horizons

Article - Nov 19, 2014 by Verification Horizons

Webinar - Nov 12, 2014 by Doug Smith

Article - Nov 11, 2014 by Verification Horizons

Demo - Oct 22, 2014 by Thomas Ellis

Webinar - Oct 16, 2014 by Doug Smith

Webinar - Oct 15, 2014 by Bob Oden

Webinar - Oct 15, 2014 by Tom Fitzpatrick