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2413 Results
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How Formal Reduces Fault Analysis for ISO 26262
Resource (Paper (.PDF)) - Feb 15, 2017 Doug Smith
This paper discusses how to use formal verification for static and transient fault analysis to generate ISO 26262 safety metrics, first describing fault pruning and then the more sophisticated fault injection using SLEC.
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Questa VRM and Jenkins
Track - Jan 10, 2017 Darron May
This track will define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.
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Jenkins Installation and Setup
Session - Jan 10, 2017 Darron May
In this session, you will be introduced to the Jenkins continuous integration system, along with step-by-step installation and setup instructions.
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Jenkins Project Configuration
Session - Jan 10, 2017 Darron May
In this session, we will walk through the project configuration and how to setup a job with the Questa VRM plug-in.
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Jenkins VRM Integration
Demo - Jan 10, 2017 Darron May
In this session, we will demo the Questa VRM Jenkins integration, and you will see firsthand how to execute tests and generate reports.
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The Fundamental Power States for UPF Modeling and Power Aware Verification
Article - Jan 04, 2017 Verification Methodology Team
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Introspection Into SystemVerilog Without Turning It Inside Out
Article - Jan 03, 2017 Dave Rich
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UCIS Applications: Improving Verification Productivity, Simulation Throughput, and Coverage Closure Process
Article - Jan 03, 2017 Verification Methodology Team
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Interpreting UPF For A Mixed-Signal Design Under Test
Article - Jan 03, 2017 Verification Methodology Team
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Is Your Power Aware Design Really X-Aware?
Article - Jan 03, 2017 Verification Methodology Team
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Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification
Article - Jan 03, 2017 Verification Methodology Team
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So You Think You Have Good Stimulus: System-Level Distributed Metrics Analysis and Results
Article - Jan 03, 2017 Andreas Meyer
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Conclusion: Deeper Dive into Non-Trivial Bug Escapes and Safety Critical Designs
Resource (Verification Horizons Blog) - Jan 03, 2017 Harry Foster
In my previous blog, I presented verification results in terms of schedules, number of required spins, and classification of functional bugs. In this blog, I conclude the series by having a little fun with some of the findings from our recent study. You might recall from our 2014 study we did a deeper dive into the findings made a non-intuitive observation related to design size and first silicon success. That is, the smaller the design the less likelihood of achieving first silicon success.
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Jenkins Tutorial - Setup, Install, Configuration
Resource (Reference Documentation) - Dec 23, 2016 Darron May
Questa VRM 10.5 has native support to allow use with the Questa VRM Jenkins plug-in. This plug-in will be made available on the Jenkins plug-in website once it is released but currently has to be installed from a file. This document gathers a few notes on how to install Jenkins, install the plug-in and set-up a demo design with Jenkins running VRM.
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JUnit Plugin (required)
Resource (Reference Documentation) - Dec 23, 2016
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Questa VRM
Resource (Reference Documentation) - Dec 23, 2016 Darron May
This plugin adds the ability for Jenkins to publish results from Questa Verification Run Manager (VRM).
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Jenkins Release
Resource (Reference Documentation) - Dec 23, 2016
The leading open source automation server, Jenkins provides hundreds of plugins to support building, deploying and automating any project.
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Dashboard View (optional)
Resource (Reference Documentation) - Dec 23, 2016
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Five Common Pitfalls to Avoid While Verifying PCIe® Based NVMe Controllers
Paper - Dec 19, 2016 Saurabh Sharma - Siemens EDA
NVMe is gaining rapidly in mindshare among consumers and vendors. Some industry analysts are forecasting that PCIe® based NVMe will become the dominant storage interface over the next few years. With its high-performance and low-latency characteristics, and its availability for virtually all platforms, NVMe is a game changer. For the first time, storage devices and storage subsystems have a fundamentally different way to operate with host computers, unlike any previous storage protocol.
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Five Common Pitfalls to Avoid while Verifying PCIe Based NVMe Controllers
Resource (Paper (.PDF)) - Dec 19, 2016 Saurabh Sharma - Siemens EDA
NVMe is an optimized, high-performance scalable host controller interface designed to address the needs of Enterprise and Client systems that utilize PCI Express-based solid-state storage. Designed to move beyond the dark ages of hard disk drive technology, NVMe is built from the ground up for non-volatile memory (NVM) technologies.
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Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
Resource (Paper (.PDF)) - Dec 19, 2016 Saumya Agrawal - Siemens EDA
The display protocol IP market is growing at a very fast pace. This is chiefly the outcome of the incredible increase in popularity of a wide variety of display source devices: such as DVD players, computer systems, and display sink/receiver devices: such as televisions, projectors, and display instruments. End users, the consumers, have also become more technologically savvy, increasing the demand for more and better products.
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The Fundamental Power States for UPF Modeling and Power Aware Verification
Resource (Paper (.PDF)) - Dec 14, 2016 Progyna Khondkar
This paper shares validation procedures for UPF strategies. Design examples and case studies demonstrate how to achieve power aware verification closure with state and transition coverage, as well as state cross-coverage of power domains and supply sets in more flexible and controllable ways.
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The Fundamental Power States for UPF Modeling and Power Aware Verification
Paper - Dec 14, 2016 Progyna Khondkar
This paper shares validation procedures for UPF strategies. Design examples and case studies demonstrate how to achieve power aware verification closure with state and transition coverage, as well as state cross-coverage of power domains and supply sets in more flexible and controllable ways. Eventually the power state concept realization allows probing further into the power management components for design and IP integration in different levels of designs, from RTL to PG-netlist.
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What is CDC Protocol Verification: Why You Absolutely Need It to Prevent Bugs in Your Silicon
Webinar - Dec 05, 2016 Kurt Takara
In this session, we discuss the pros and cons of various approaches to verifying Clock-Domain Crossing (CDC) protocols and we show how Questa CDC automatically generates protocol assertions.
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What is CDC Protocol Verification: Why You Absolutely Need It to Prevent Bugs in Your Silicon
Resource (Slides (.PDF)) - Dec 05, 2016 Kurt Takara
In this session, we discuss the pros and cons of various approaches to verifying CDC protocols and we show how Questa CDC automatically generates protocol assertions.