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Integrate Ethernet QVIP in a Few Hours: an A-to-Z Guide

Article - Nov 01, 2014 by Prashant Dixit - Siemens EDA

Functional verification is critical in the development of today's complex digital designs. Increasing hardware complexity generally tracks Moore's Law; however, verification complexity grows at an even faster rate. Verification cycle is widely acknowledged as the major bottleneck in design methodology. Up to 70 percent of design time and resources are spent on functional verification. And yet, functional bugs are the number one cause of silicon re-spins.
Fast Track to Productivity Using Questa Verification IP

Article - Nov 01, 2014 by Dave Aerne

This article demonstrates these features while referencing the PCIe and AXI4 Questa VIP components.
Cache Coherent Interface Verification IP

Article - Nov 01, 2014 by Amit Kumar Jain - Siemens EDA

In a multi-processor system, a cache coherence protocol is vital to maintain data consistency between local caches and the main memory. With the local processor cache, the bus stimulus must be compliant with the cacheline state following predefined ordering rules between the read/write and cache snoop stimulus. These constraints can make it confusing to generate stimulus. This article addresses such stimulus generation issues by providing easy to use generic APIs along with a cache controller.
Hey You, Design Engineer!

Article - Nov 01, 2014 by Josh Rensch - Siemens EDA

How design engineers can get verification engineers to stop complaining, and other advice.
Please! Can Someone Make UVM Easier to Use?

Article - Nov 01, 2014 by Rich Edelman

UVM was designed as a means of simplifying and standardizing verification which had been fragmented as a result of many methodologies in use like eRM, VMM, OVM. It started off quite simple. Later on, as a result of feature creep, many of the issues with the older methodologies found its way into UVM. This article looks at some of those issues and suggests ways of simplifying the verification environment.
Controlling On-the-Fly-Resets in a UVM-Based AXI Testbench

Article - Nov 01, 2014 by Sundar Raman Arunachalam - VeriKwest Systems

This article describes techniques for modeling UVM testbench components in an AXI-based environment. It also covers handling the stimulus generation unit (uvm_test) required to re-generate the DUT traffic without using phase jumps. Note that this technique can be applicable to other UVM-based testbench environments.
Increase Verification Productivity with Questa UVM Debug

Article - Nov 01, 2014 by Dr. Mike Bartley

Debug is one of the major bottlenecks that verification teams face today. Traditionally, to make the debug task easier, significant effort is invested upfront by following standard coding guidelines and writing code that is debug friendly. The near-universal adoption of UVM has, while making the verification process a lot more streamlined, however, increased the debug challenge.
Questa Coverage Closure

Demo - Oct 22, 2014 by Thomas Ellis

In this demo, you will learn a few of the key features of the Questa Verification Platform as applies to the process of coverage closure.
Introduction to Questa CoverCheck

Webinar - Oct 16, 2014 by Doug Smith

In this session, you will learn how Questa CoverCheck automates and accelerates the process of code coverage closure.
Establishing a Company Wide Verification Reuse Library

Webinar - Oct 15, 2014 by Bob Oden

In this session, you will learn how to outline key characteristics of a reuse verification library and will outline a proven reuse methodology.
Navigating the Perfect Storm: New School Verification Solutions

Webinar - Oct 15, 2014 by Tom Fitzpatrick

This session introduces today’s trends and challenges in SoC design and verification and outlines a path for navigating this “perfect storm."
Verification and Debug: Old School Meets New School

Webinar - Oct 15, 2014 by Rich Edelman

You will learn how to use the best of old and new school debug techniques to find problems faster and to better answer “am I done yet”.
UVM Sequences in Depth

Webinar - Aug 12, 2014 by Tom Fitzpatrick

In this session, we will walk through the mechanics of setting up and executing Slave Sequences in a responder.In this session, we will walk through the mechanics of setting up and executing Slave Sequences in a responder. We will also walk through modeling an interrupt sequence and show how to have interrupt sequences running in conjunction with other stimulus sequences.
Overview and Welcome

Session - Aug 06, 2014 by Ray Salemi

This session describes rudimentary SystemVerilog through writing a complete UVM testbench.
Lab and Code Examples

Resource (Tarball) - Aug 06, 2014 by Ray Salemi
Introduction to UVM - Overview and Welcome

Resource (Slides (.PDF)) - Aug 06, 2014 by Ray Salemi
SystemVerilog Primer for VHDL Engineers

Session - Aug 06, 2014 by Ray Salemi

This session teaches SystemVerilog using concepts from VHDL.
SystemVerilog Primer for VHDL Engineers

Resource (Slides (.PDF)) - Aug 06, 2014 by Ray Salemi
Object Oriented Programming

Resource (Slides (.PDF)) - Aug 06, 2014 by Ray Salemi
Object Oriented Programming

Session - Aug 06, 2014 by Ray Salemi

This session introduces object oriented programming and will teach you the basics to be able to use the UVM.
SystemVerilog Interfaces

Resource (Slides (.PDF)) - Aug 06, 2014 by Ray Salemi
SystemVerilog Interfaces

Session - Aug 06, 2014 by Ray Salemi

This session teaches you how to use SystemVerilog interfaces.
Packages, Includes and Macros

Resource (Slides (.PDF)) - Aug 06, 2014 by Ray Salemi
Packages, Includes and Macros

Session - Aug 06, 2014 by Ray Salemi

SystemVerilog has a variety of tools for controlling code and sharing definitions. This session examines these in detail.
UVM Components and Tests

Resource (Slides (.PDF)) - Aug 06, 2014 by Ray Salemi