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Parameterized UVM Tests
Resource (Pattern) - May 02, 2016 by Harry Foster
Parameters used in a design in most cases must also be used in a testbench to ensure proper connections and communication can be performed. Parameterized UVM tests (which are not available by default) provide an easy mechanism for sharing of parameters.
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Classes
Session - Apr 27, 2016 by Dave Rich
This session provides a short history of OOP and explains some of the terminology used by SystemVerilog that enables it.
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Classes
Resource (Slides (.PDF)) - Apr 27, 2016 by Dave Rich
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Inheritance and Polymorphism
Session - Apr 27, 2016 by Dave Rich
This session explains the key features and benefits of inheritance, polymorphism, and virtual methods along with examples of their use.
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Inheritance and Polymorphism
Resource (Slides (.PDF)) - Apr 27, 2016 by Dave Rich
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OOP Design Pattern Examples
Resource (Slides (.PDF)) - Apr 27, 2016 by Dave Rich
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OOP Design Pattern Examples
Session - Apr 27, 2016 by Dave Rich
This session provides examples of design patterns along with parameterized classes extensively used by people writing re-usable verification environments with the UVM.
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Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs
Resource (Slides (.PDF)) - Apr 13, 2016 by Joe Hupcey
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Questa Visualizer - Power Aware Debug
Demo - Mar 18, 2016 by Chuck Seeley
In this demo, you will learn the UPF based Power Aware Debug features available in Visualizer with Questa PASim.
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Introducing the Verification Academy Patterns Library!
Resource (Verification Horizons Blog) - Mar 16, 2016 by Harry Foster
If you have been involved in either software or advanced verification for any length of time, then you probably have heard the term Design Patterns . In fact, the literature for many of today’s testbench verification methodologies (such as UVM) often reference various software or object-oriented related patterns in their discussions.
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Walking
Resource (Pattern) - Mar 16, 2016 by Harry Foster
The walking pattern will be applicable for anyone focused on integration verification to effectively verify connectivity between various modules such as Address and Data bus. These are very commonly patterns used in stimulus and verification of RAM address and bus connectivity.
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Strategy
Resource (Pattern) - Mar 16, 2016 by Harry Foster
This pattern helps implement one of the basic principles of Object Oriented programming and defines a family of algorithms, encapsulate each one, and make them interchangeable. Strategy lets the algorithm vary independently from clients that use it.
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No RTL Yet? No Problem - UVM Testing a SystemVerilog Fabric Model
Resource (Paper (.PDF)) - Mar 15, 2016 by Rich Edelman
SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.
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Verifying Display Standards – A Comprehensive UVM-based Verification IP Solution
Paper - Mar 12, 2016 by Saumya Agrawal - Siemens EDA
The display protocol IP market is growing at a very fast pace. This is chiefly the outcome of the incredible increase in popularity of a wide variety of display source devices: such as DVD players, computer systems, and display sink/receiver devices: such as televisions, projectors, and display instruments. End users, the consumers, have also become more technologically savvy, increasing the demand for more and better products.
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An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
Article - Mar 02, 2016 by Shaela Rahman - Baker Hughes
FPGA designs are becoming too large to verify by visually checking waveforms, as the functionality has become beyond easy comprehension.
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First Time Unit Testing Experience Report with SVUnit
Article - Mar 02, 2016 by Neil Johnson
Verification teams don’t typically verify testbench components. But this Qualcomm Technologies IP team realized the necessity of unit testing a critical testbench component and the corresponding debug time and frustration it could prevent for downstream IP and chip teams.
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The Verification Academy Patterns Library
Article - Mar 02, 2016 by Harry Foster
The literature for many of today’s testbench verification methodologies (such as UVM) often reference various software or object-oriented related patterns in their discussions. For example, the UVM Cookbook (available out on the Verification Academy) references the observe pattern when discussing the Analysis Port .
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Increased Efficiency with Questa VRM and Jenkins Continuous Integration
Article - Mar 02, 2016 by Thomas Ellis
For all the incredible technological advances to date, no one has found a way to generate additional time. Consequently, there never seems to be enough of it. Since time cannot be created, it is utterly important to ensure that it is spent as wisely as possible.
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Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
Article - Mar 02, 2016 by Saumya Agrawal - Siemens EDA
The display protocol IP market is growing at a very fast pace. This is chiefly the outcome of the incredible increase in popularity of a wide variety of display source devices: such as DVD players, computer systems, and display sink/receiver devices: such as televisions, projectors, and display instruments. End users, the consumers, have also become more technologically savvy, increasing the demand for more and better products.
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Nine Effective Features of NVMe® Questa Verification IP to Help You Verify PCIe® Based SSD Storage
Article - Mar 02, 2016 by Saurabh Sharma - Siemens EDA
This article provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to conventional technologies, and point out key areas to focus on during its verification. In particular, we will describe how NVMe Questa ® Verification IP (QVIP) effectively contributes and accelerates verification of PCIe-based SSDs that use NVMe interfaces.
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MIPI C-PHY™: Man of the Hour
Article - Mar 02, 2016 by Yogesh Chaudhary - Siemens EDA
The MIPI Alliance signature dishes, C-PHY™ and D-PHY™, are becoming favorite dishes of the imaging industry. These interfaces allow system designers to easily scale up the existing MIPI Alliance Camera Serial Interface (CSI-2™) and Display Serial Interface (DSI™) ecosystems to support higher resolution image sensors and displays while keeping low power consumption at the same time. This gives them an edge to get more into the mobile systems with bigger and better pictures.
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Total Recall: What to Look for in a Memory Model Library
Article - Mar 02, 2016 by Mark Peryer
Almost all electronics systems use memory components, either for storing executable software or for storing data. Accurate memory models are fundamental. Making these models available in proven, standards-based libraries is essential to functional verification of these kinds of designs.
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Certus™ Silicon Debug: Don’t Prototype Without It
Article - Mar 02, 2016 by Doug Amos - Siemens EDA
Traditional FPGA debuggers might be acceptable for single FPGA designs, or where long instrumentation iterations might somehow be tolerable, but they run out of steam when faced with a full-scale, FPGA prototype of today's complex SoCs. Certus Silicon Debug is ready to take up the baton and provide prototypers with the visibility and productivity they demand.
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Simplified UVM for FPGA Reliability: UVM for “Sufficient Elemental Analysis” in DO-254 Flows
Article - Mar 02, 2016 by Shashi Bhutada - Siemens EDA
DO-254 and other safety critical applications require meticulous initial requirements capture followed by accurate functional verification. “Elemental Analysis” in DO-254 refers to the verification completeness to ensure that all ‘elements’ of a design are actually exercised in the pre-planned testing. Code Coverage is good for checking if implementation code has been tested, but cannot guarantee functional accuracy.
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Complex Signal Processing Verification under DO-254 Constraints
Article - Mar 02, 2016 by François Cerisier - AEDVICES Consulting
This article describes a combined requirement and metric driven methodology developed at a customer site for the verification of a complex signal processing SoC block under DO-254 constraints. This methodology also enables both horizontal and vertical reuse of the tests, allowing tests to run both in IP simulation and on FPGA boards at SoC level. This approach is described in a generic way and can be applied to different signal or data processing designs.